Engr. Annalyn D.

Soria
 Schematic data files (.sdb) describing the circuits
to be analyzed in graphical form, for display and
editing by S-Edit™ Schematic Editor.
 Simulation input files (.sp) describing the circuits
to be analyzed in textual form, for editing and
simulation by T-Spice™ Circuit Simulator. (The
listings of input files in this chapter exclude
comments.)
 Simulation output files (.out) containing the
numerical results of the circuit analyses, for
manipulation and display by W-Edit™ Waveform
Viewer.
 Launch T-Spice
 Use File > Open to open the specified SPICE
(.sp) file.
 Use Simulation > Run Simulation to start the
simulation.
 In the Run Simulation dialog, under Waveform
options choose Show during.
 Click Start Simulation. W-Edit will
automatically display the results.
 DC operating point analysis finds a circuit’s
steady-state condition, obtained (in principle)
after the input voltages have been applied for
an infinite amount of time.
 Schematic invert1.sdb
 Input invert1.sp
 Output invert1.out
 c2 out Gnd 800ff .include ml2_125.md
 m1p out in Vdd Vdd pmos L=5u W=12u
 m1n out in Gnd Gnd nmos L=5u W=8u
 .op
 Vdd Vdd Gnd 3.0
 vin in Gnd 1.0
 .END
 A capacitor c2 (signified by the key letter c),
connecting nodes out and GND, is defined,
with a capacitance of 800 femtofarads.

 The .include command causes T-Spice to

read in the contents of the model file
ml2_125.md for the evaluation of transistors
m1n and m1p. This file (which must be in the
same directory as invert1.sp) consists of two
.model commands, describing two MOSFET
models called nmos and pmos:
 .model nmos nmos
 + Level=2 Ld=0.0u Tox=225.00E-10
 + Nsub=1.066E
 +16 Vto=0.622490 Kp=6.326640E-05
 + Gamma=.639243 Phi=0.31 Uo=1215.74
 + Uexp=4.612355E-2 Ucrit=174667 Delta=0.0
+ Vmax=177269 Xj=.9u Lambda=0.0
 + Nfs=4.55168E+12 Neff=4.68830
Nss=3.00E+10
 + Tpg=1.000 Rsh=60 Cgso=2.89E-10
 + Cgdo=2.89E-10 Cj=3.27E-04 Mj=1.067
 + Cjsw=1.74E-10 Mjsw=0.195
 .model pmos pmos
 + Level=2 Ld=.03000u Tox=225.000E-10
 + Nsub=6.575441E
 +16 Vto=-0.63025 Kp=2.635440E-05
 + Gamma=0.618101 Phi=.541111 Uo=361.941
+ Uexp=8.886957E-02 Ucrit=637449 Delta=0.0
+ Vmax=63253.3 Xj=0.112799u Lambda=0.0
 + Nfs=1.668437E+11 Neff=0.64354
Nss=3.00E+10
 + Tpg=-1.000 Rsh=150 Cgso=3.35E-10
 + Cgdo=3.35E-10 Cj=4.75E-04 Mj=.341
 + Cjsw=2.23E-10 Mjsw=.307
 Two transistors, m1n and m1p, are defined in
invert1.sp. These are MOSFETs, as indicated
by the key letter m which begins their names.
Following each transistor name are the names
of its terminals. The required order of
terminal names is: drain–gate–source–bulk.
Then the model name (nmos or pmos in this
example), and physical characteristics such as
length and width, are specified.
 The .op command performs a DC operating
point calculation and writes the results to the
file specified in the
◦ Simulate > Start Simulation dialog.
 Two voltage sources are defined: Vdd, which
sets node Vdd to 3.0 volts relative to system
ground, and vin, which sets node in to 1.0
volt relative to ground.
 The output file lists the DC operating point
information for the circuit described by the
input file:
 DC ANALYSIS v(out) = 2.9309e+00
 v(in) = 1.0000e+00
 v(Vdd) = 3.0000e+000
 i(Vdd) = -5.8215e-006
 i(vin) = 0.0000e+000
 DC transfer analysis is used to study the
voltage or current at one set of points in a
circuit as a function of the voltage or current
at another set of points. This is done by
sweeping the source variables over specified
ranges, and recording the output.
 Schematic invert2.sdb
 Input invert2.sp
 Output invert2.out
 .include ml2_125
 .md m1n out in GND GND nmos l=5u w=8u
m1p out in vdd vdd pmos l=5u w=12u
 c2 out GND 800ff vdd
 vdd GND 3.0
 vin in GND 1.0
 .dc vin 0 3 0.02 vdd 2 4 0.5
 .print dc in out
 The .dc command, indicating transfer analysis, is
followed by a list of sources to be swept, and the
voltage ranges across which the sweeps are to
take place.
 In this example, vin will be swept from 0 to 3
volts in 0.02 volt increments, and vdd will be
swept from 2 to 4 volts in 0.5 volt increments.
 The transfer analysis will be performed as
follows: vdd will be set at 2 volts and vin will be
swept over its specified range; vdd will then be
incremented to 2.5 volts and vin will be reswept
over its range; and so on, until vdd reaches the
upper limit of its range.
 The .dc command ignores the values
assigned to the voltage sources vdd and vin
in the voltage source statements, but they
must still be declared in those statements.
 The results for nodes in and out are reported
by the .print dc command to the specified
destination.
 Transient analysis provides information on
how circuit elements vary with time.
 The basic T-Spice command for transient
analysis has three modes. In the default
mode, the DC operating point is computed,
and T-Spice uses this as the starting point for
the transient simulation.
 .include ml2_125
 .md m1n out in GND GND nmos l=5u w=8u
m1p out in vdd vdd pmos l=5u w=12u
 c2 out GND 800ff
 vdd vdd GND 3.0
 vin in GND PWL(0ns 0V 100ns 0V 105ns 3V
200ns 3V 205ns 0V 300ns
 + 0V 305ns 3V 400ns 3V 405ns 0V 500ns 0V
505ns 3V 600ns 3V)
 .tran 2n 600n
 .print tran in out
 voltage source vin, instead of setting the voltage between nodes
in and GND at a constant value, here generates a piecewise linear
waveform input (indicated by the keyword PWL) to in.
 The successive “legs” of the waveform are delimited by the
corners, whose times and voltages are specified in the
arguments to PWL. Between 0 and 100 nanoseconds, the voltage
at in is zero; between 100 and 105 nanoseconds, the voltage is
linearly interpolated (ramps up) between 0 and 3; between 105
and 200 nanoseconds, the voltage stays at 3; and so on.
 The parameters of the device statement that defines vin are
continued to the next line with the + character in the first
column.
 The .tran command specifies the characteristics of the transient
analysis to be performed: it will last for 600 nanoseconds, with
time steps no larger than 2 nanoseconds.