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Chapter 4

Assembly Language
Programming
Steps involved in Programming
1. Specifying the problem

2. Designing the problem – solution: the exact step by step process that is to
be followed (program logic) is developed and written down.

3. Coding : once the program is specified and designed, it can be

implemented. Implementation begins with the process of coding the
program.

4. Debugging : is the process of testing the code to see if it does the given
task.

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Flowchart
 start/stop operation

 flow with direction

 input/output

 decision

 predefined process (subroutine)

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Label : Mnemonic Operand1, Operand2 ; comment

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Assembly Language Programming Tips
 Optimum Solution : the solution which takes minimum memory space for the program
and minimum time for the execution of a task.
 Proper Instructions : INC BX is a single byte instruction which require 2 clock cycles for
execution. ADD BX, 0001H is a 4 byte instruction which require 4 clock cycles for
execution.
 Advanced Instruction :

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 Proper Addressing Modes : it is advisable to store most of the operands in the CPU.

 Prepare documentation :
 Description of the purpose of the program module.
 In case of subroutine program list of passing parameters and return value.
 Register and memory locations used.
 Proper comments for each instruction used.
Timing and Delays
 In the real time applications, such as traffic light control, digital clock, process control,
serial communication, it is important to keep a track with time.
 For example in traffic light control application, it is necessary to give time delays
between two transitions.
 These time delays are in few seconds and can be generated with the help of
executing group of instructions number of times. This software timers are also called
time delays or software delays.

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Timer
» Delay using NOP Instruction
 NOP Instruction takes 3 clock cycles of processor time to execute. So by executing
NOP instruction in between two instructions we can get delay of 3 clock cycles.
Timer delay using Counters
clock cycles required
MOV CX, COUNT 4
BACK : DEC CX 2
JNZ BACK 16/4
Total cycles required to execute the given program = 4 + (count - 1) * (2 + 16) + (2 + 4 )
Example 1
For count = 100, the number of clock cycles required are
4 + (100 - 1) * (2 + 16) + (2 + 4) = 1792
Assuming the operating frequency of 8086 system 10 MHZ,
Time required for 1 clock cycle = = 0.1μsec
Total time = 1792=(1792*0.1) μsec
Example 2
Calculate the number of count required to generate a delay of 50ms.
Number of required clock cycles =
= = 500 000
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Count
» = +1
= +1
≈ 27778 = 6C82H
Timer delay using Nested Loops
 In this program one or more external loop is added to execute the internal loop
multiple times. So that we can get larger delays.
MOV BX, MULTIPLIER COUNT
REPE : MOV CX, COUNT
BACK : DEC CX
JNZ BACK
DEC BX
JNZ REPE
 In the calculations of nested loops, the delay introduced by inner loop is very large in
comparison with the delay provided by the other instructions. Therefore it is not
necessary to consider the last loop for the external loop delay calculations separately.
Total clock cycles required to execute the given program = [ 4 + (count - 1)x(2 + 16) + (2 + 4)] x multiplier count

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Example
» 3
For count = 100 and multiplier count 50, the number of clock cycles required are
[ 4 + (100 - 1) x (2 + 16) + (2 + 4)] x 50 = 89600
Assuming operating frequency of 8086 system 10 MHZ,
Total time required for execution of a given program = 89600 x 0.1μsec = 8.96ms
Example 4
Write an 8086 ALP to generate a delay of 100ms, if 8086 system frequency is 10 MHZ.
MOV CX, COUNT
BACK : DEC CX
JNZ BACK

NUMBER OF REQUIRED CLOCK CYCLES = = = 1000 000

Count = + 1 = + 1 = 55556 = D904H
Example 4
Write an 8086 ALP to generate a delay of 1 minute if 8086 system frequency is 10MHZ.

MOV BX, MULTIPLIER COUNT

REPE : MOV CX, COUNT
BACK : DEC CX
JNZ BACK
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DEC BX
JNZ REPE
Delay generated by inner loop with maximum count (FFFFH = 65535)
» = [4 + (65535 - 1) x (2 + 16) + (2 + 4)] x 0.1μs = 118.1422msec
Multiplier count = = ≈ 509 = 1FDH

Programming with Assembler

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Some Assembly Language Example Programs

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DOS and BIOS Interrupts
 In IBM PC, part of the operating system is located in the permanent memory (ROM) and part is
loaded during power up.
 The part located in ROM is referred to as ROM-BIOS. The other part which is loaded in RAM
during power-up from hard disk or floppy disk is known as DOS.
 BIOS is located in an 8K-byte ROM at the top of memory, the address range being from FE000H
to FFFFFH.
 The ROM-BIOS contains routines for power-on self test, system configuration analysis, time of
day, print screen, bootstrap loader, i/o support program for asynchronous communication,
keyboard, diskette, printer and display.
 There are some extremely useful subroutines within BIOS and DOS that are available to the
user through the INT (interrupt) instruction.
 The INT instruction is somewhat like a FAR call. When it is invoked, it saves CS:IP and the flags
on the stack and goes to the subroutine associated with that interrupt.
INT xx ; the interrupt number xx can be 00 – FFH
 Before the service of INT is requested, certain registers must have specific values in them,
depending on the function being requested.
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 INT 21H is provided by DOS in contrast to INT 10H, which is BIOS-ROM based. When MS-DOS is
loaded into the computer, INT 21H can be invoked to perform some extremely useful functions.
These functions are commonly referred to as DOS INT 21H function calls.

INT 21H option 09: outputting a string of data to the monitor

AH=09 DX=offset address of the data to be displayed

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INT 21H option 02: outputting a single character to the monitor
AH=02 DL= character to be displayed
MOV AH, 02
MOV DL, ‘K’
INT 21H

INT 21H option 01: inputting a single character, with echo

AH=01 after interrupt, the input character will be in AL
MOV AH, 01
INT 21H

INT 21H option 0AH: inputting a string of data from a keyboard

AH=0AH DX=offset address at which the data will be stored
Data1 DB 6, ?, 6 DUP (FF)
MOV AH, 0AH
MOV DX, OFFSET Data1
INT 21H 17
Use of carriage return and line feed

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INT 21H option 07: keyboard input without echo
AH=07 AL=input character in ASCII form
MOV AH, 07
INT 21H

INT 21H option 2CH: get system time

MOV AH, 2CH
INT 21H ; CH=hour, CL=minute, DH=second, DL=hundredth of second

INT 21H option 2DH: set system time

AH=2DH CH=hour CL=minute DH=second DL=hundredth of a second
MOV AH, 2DH
MOV CH, 0BH
MOV DH, 0
MOV DL, 0
INT 21H

INT 21H option 4CH: terminate the program(exit)

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MOV AH, 4CH
INT 21H
Reentrant Procedure
 In some situations it may happen that procedure1 is called from main program, procedure2
is called from procedure 1 and procedure1 is again called from procedure2.
 In this situation program execution flow reenters in the procedure1. this type of procedures
are called reentrant procedures.

Recursive Procedure
 A recursive procedure is a procedure which calls itself. It is used to work with complex data
structure called tree.

Macro
 Macro is a group of instructions. The assembler generates the code in the program each time
where the macro is called.
 It is important to note that macro sequences execute faster than procedures because there are
no CALL and RET instructions to execute. The assembler places the macro instructions in the
program each time when it is invoked. This is known as macro expansion.

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 A local variable defined in the macro is available in the macro, however it is not available
outside the macro.

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Instruction Formats
 The instructions of 8086 vary from 1 to 6 bytes in length. For each instruction format first field
is operation code field, commonly known as op-code field.
 Op-code field indicates the type of operation to be performed by the processor.

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W-bit
 The w-bit specifies whether instruction is a byte instruction (W=0) or a word instruction (W=1).
D-bit
 Indicates that the register specified within the instruction is a source register (D=0) or
destination register (D = 1).
S-bit
 An 8-bit 2’s complement number can be extended to a 16-bit 2’s complement number by
making all of the bits in the higher-order byte equal the most significant bit in the low order
byte.
V-bit
 Decides the number of shifts for rotate and shift instructions. If V=0, then count=1; if V=1, the
count is in CL register.
Z-bit
 Is used for string primitives such as REP for comparison with ZF flag. If it is 1, the instruction
with REP prefix is executed until the zero flag matches the Z-bit.

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Example 1:
Write the instruction format for PUSH BX instruction given the op-code for PUSH instruction is
01010.
Solution:

Example 2:
Write the instruction format for MOV AX, CX given the op-code for MOV instruction is 100010.
Solution

Example 3:
Write the instruction format for MOV 56[SI], BH given the op-code for MOV instruction is 100010.
Solution

Example 4:
Write the instruction format for MOV DL, [BX]
Solution

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System Configuration of 8086 Microprocessor

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Signal Description of 8086
 8086 and 8088 microprocessors can be operated in two modes: Minimum mode and
Maximum mode.
 The minimum mode is used for small systems with a single processor and maximum mode is
used for medium size to large systems, which often include two or more processors.
 The 8086 signals can be categorized in three groups : signals having common functions in
both minimum and maximum modes, signals having special functions for minimum mode
and signals having special functions for maximum mode.
Signals with common functions in both modes
1. AD0 – AD15 : acts as address bus during the first part of machine cycle and data bus for the
remaining part of the machine cycle.
2. A16/S3 – A19/S6 : during the first part of machine cycle these are used to output upper 4-bits
of address. During remaining part of the machine cycle these are used to output status,
which indicates the type of operation to be performed in that cycle. S3 and S4 indicate the
segment register being used , S5 gives the current setting of the interrupt flag (IF) and S6 is
always zero.

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3. /S7 : BHE(bus high enable) : low on this pin during first part of the machine cycle, indicates
» that at least one byte of the current transfer is to be made on higher order byte AD15-AD8,
otherwise the transfer is made on lower order byte AD7-AD0. status S7 is output during the
later part of the machine cycle, but, presently, it has not been assigned a meaning.

4. NMI : it is a positive edge triggered non maskable interrupt request.

5. INTR : is a level triggered maskable interrupt request. It is sampled during the last clock cycle
of each instruction to determine if the processor should enter into an interrupt service
routine.
6. CLK : 8086 requires clock signal (with 33% duty cycle) from some external, crystal controlled
generator to synchronize internal operations. Clock frequency depends on the version of
8086.

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7. RESET : it clears IP, DS, SS, ES and the instruction queue. It then sets CS to FFFFH. This signal
» must be high for at least 4 clock cycles. When RESET is removed, 8086 will fetch its next
instruction from physical address FFFF0H.
8. READY : if this signal is low the 8086 enters into wait state. This signal is used primarily to
synchronize slower peripherals with the microprocessor.
9. (input) : this signal is only used by the WAIT instruction. The 8086 enters into a wait state
after execution of the WAIT instruction until a LOW signal on the pin. signal is synchronized
internally during each clock cycle on the leading edge of the clock cycle.
10. (output) : is low whenever the 8086 is reading data from memory or an I/O device.
11. MN/ (input) : used to configure minimum mode or maximum mode. This pin is tied high for
minimum mode.

Signal Definitions for Maximum mode

12. INTA (interrupt acknowledge) output : this indicates recognition of an interrupt request. It
consists of two negative going pulses in two consecutive bus cycles. The first pulse informs
the interface its request has been recognized and upon receipt of the second pulse, the
interface is to send the interrupt type to the processor over the data bus.
13. ALE (Address Latch Enable) output : this signal is provided by 8086 to de multiplex the AD0 –
AD15 into A0-A15 and D0-D15 using external latches.
14. (data enable) output : this signal informs the transceivers that the CPU is ready to send or
receive data.
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4. DT / (data transmit/receive) output : this signal is used to control data flow direction. High
» on this pin indicates that the 8086 is transmitting the data and low indicates that the 8086 is
receiving the data.
5. M / output : is used to distinguish memory data transfer, (M / = high) and I /O data transfer
(M / = low).
6. (write) output : it is low whenever the 8086 is writing data into memory or an I /O device.
7. HOLD input, HLDA output : a high on HOLD pin indicates that another master (DMA) is
requesting to take over the system bus. On receiving HOLD signal processor outputs HLDA
signal HIGH as an acknowledgment. At the same time, processor tristates the system bus. A
low on HOLD gives the system bus control back to the processor. Processor then outputs low
signal on HLDA.

Signal definitions for maximum mode

8. QS0, QS1 (output) : these two output signals reflect the status of the instruction queue. It
indicates the activity in the queue during the previous clock cycle.

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2. , , (output) : these status signals indicate the type of transfer to be take place during the
» current bus cycle.

3. : this signal indicates that an instruction with a lock prefix is being executed and the bus is
not to be used by another processor.
4. / and / : in the maximum mode, HOLD and HLDA pins are replaced by (bus request) / (bus
grant), and / signals. By using bus request signal another master can request for the system
bus and processor communicate that the request is granted to the requesting master by using
bus grant signal. Both signals are similar except the / has higher priority than / .

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Thank You!!!

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