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Pin diagram of 8086

• Out of 40 pins, 32 have the same functions in
MIN mode and MAX mode.

• Remaining 8 have different functions in

Minimum mode and Maximum mode.
AD 0 – AD 15 (I/O)
• These lines are multiplexed
bidirectional address/ data bus.

• During T1 state of machine

cycle, they carry lower order 16
bits of address.

• In the remaining clock cycles

they carry 16 bit data.

• AD0-AD7 carry the lower order

byte of data and AD8 – AD15
carry the higher order byte of
A19/S6, A18/S5, A17/S4, A16/S3 (O)
• These lines are multiplexed
unidirectional (output) address
and status lines.

• During state T1, they carry higher

order 4 bits of address.
• In the remaining clock cycles they
carry status signals.
• After the first clock cycle of an instruction
execution, the S4 and S3 pins specify which
segment register generates the segment portion of
the 8086 address.
• Thus by decoding these lines and using the
decoder outputs as chip selects for memory
chips, up to 4 Megabytes (one Mega per
segment) of memory can be accessed.

• This feature provides a degree of protection

by preventing write operations to one
segment from erroneously overlapping into
another segment and destroying information
in that segment.
S6, S5
• S6 is always at logic 0 and S5 provides the
status of the 8086 interrupt enable flag.
BHE*/ S7 (Bus High Enable) - O

• During first clock cycle (T1 of machine cycle),

the 8086 uses this pin to send out BHE* .

• During the subsequent clock cycles, 8086 sends

0 on S7.

• It is a spare status line.

• Physically in 8086, the main memory can be
viewed as 2 banks of 512 Kbytes.

• The banks are called lower and upper banks.

• To select a location in these banks, a 19 bit address

is sent by 8086 on A1 – A19.

• The lower banks contains bytes with only even

addresses(like 0,2,4,..)
• The lower bank is selected by A0.
• The upper bank contains bytes only with odd

• The upper bank is selected by BHE*.

• D0-D7 is connected to lower bank and D8-D15 is

selected by upper bank.
• Whenever the 8086 needs to get
information from a memory or I/O
device , it activates the RD* pin.

• RD* pin is active low and shows

the state for T2 and T3 states and
the Tw states of any read cycle.

• This signal floats to tri-state in

"hold acknowledge cycle".
• This is an acknowledgement signal
from a slower I/O device or memory
to get extra time for data transfer.

• When high, it indicates that the

device is READY to transfer data.

• When low, the 8086 has to wait by

inserting WAIT states to the
execution cycle.
• The TEST* i/p is tested by the WAIT instruction.

• If TEST* pin = 0, nothing happens and the next

instruction executes.

• if TEST* pin = 1 the microprocessor goes to idle

state and waits for the pin to return to a logic 0
• It is a maskable interrupt.

• INTR must be high until it is


• When an external device activates

this pin, 8086 will be interrupted
only if the Interrupt Flag is enables
(using STI)

• It is an edge triggered input.

• A transition from LOW to HIGH initiates the

interrupt at the end of the current instruction.

• NMI has higher priority that INTR.

• NMI is not affected by STI or CLI.


• RESET causes the processor to immediately

terminate its present activity.

• The signal must be active HIGH for at least

four clock cycles.

• It restarts execution when the RESET returns

• The instruction queue, PSW, DS,SS, ES, IP all get
cleared and CS becomes FFFFh.

• After RESET, he first instruction will be executed

from FFFF0h.
• The clock input provides basic timing for the
processor operation and bus control activity.

• It is an asymmetric square wave with 33% duty


• The range of frequencies for different versions of

8086 range from 5MHz to 10 MHz.
• The logic level of this pin decides whether the
processor will operate in minimum mode or
maximum mode.

• The minimum mode is selected by applying logic

1 to the MN / MX* input pin. This is a single
microprocessor configuration.
• The maximum mode is selected by applying logic
0 to the MN / MX* input pin. This is a multi
micro processors configuration.
• In minimum mode, the 8086 is the only processor
in the system.

• 8086 directly generates all the control signals in

the system.
• This signal controls the direction of data flow
through the transceiver.

• When the signal is high, data is sent out

(Transmit) and when the signal is low, data is

• The DT/R* pin is connected to DIR pin of buffer.

• It is an active low signal. Used to enable the
data buffers.

• When the processor is sending out address

on A0 – A15, these addresses should not be
sent by the buffers on the data bus.
• It is an active high signal and remains high during
T1 state of machine cycle.

• It indicates that valid address is available on AD0-


• Therefore, the address sent during T1 is latched,

so that it is available to memory or I/O port
during entire machine cycle.
M/IO* (O)
• This signal is issued by the processor to distinguish
memory access from I/O access.

• When pin is high, memory is accessed.

• When pin is low, I/O is accessed.

• Indicates that the processor is performing a
write memory or write IO cycle, depending
on the state of the M /IO signal.

• WR is active for T2, T3 and TW of write cycle.

• It is active LOW, and floats to tri state during

local bus "hold acknowledge ".
• It is an active low pin.

• When the signal goes low, it means that the

processor has accepted the interrupt.
• The hold input requests DMA.

• If the HOLD signal is a logic 1, the processor

stops executing software and places its
address, data and control bus in high
impedance state.

• If HOLD pin is logic 0, the processor executes

software normally.
• Hold acknowledge indicates that 8086 has
entered the HOLD state.
Maximum Mode
• It is necessary to use maximum mode if the
processor is to be used in multiprocessor

• The most important issues in multiprocessor

environment are inter-processor communication
and bus contention.
• In this mode most of the control signals are not
obtained from the processor, but will have to be
generated from an external chip called bus

• The ALE, INTA*, DEN, DT/R* are all generated by

• In max mode, the 8288 bus controller uses the
signals S2,S1 and S0 to generate all the bus
control and command output signals required for
bus cycle.

• These status lines reflect the type of operation

being carried out by the processor.
• These signals become active during T4 of the
previous bus cycle and remain active during
T1 and T2 of the current bus cycle.

• The status lines return to passive state during

T3 of the current bus cycle, so that they may
again become active for the next bus cycle
during T4.
• In a maximum mode configuration, the
minimum mode HOLD, HLDA interface is also

• These two are replaced by request/grant lines

RQ0/ GT0 and RQ1/GT1, respectively.

• They provide a prioritized bus access

mechanism for accessing the local bus.

• RQ0/ GT0 has higher priority than RQ1/GT1.

• In minimum mode, HOLD is for bus request
and HLDA is for bus grant.

• Here both actions are performed by the same


• Also here the requests and grants are more

likely for communicating with other
processors rather than for DMA operations.
• The request / grant sequence is as follows:

1) A pulse one clock pulse wide from another bus

master requests the bus access to 8086.

2) During T4 (of current cycle) or T1 (of next clock

cycle), a pulse one clock wide from 8086 to the
requesting master, indicates that requesting
processor can use the bus.

3) When this processor is ready to release the bus, it

sends a pulse of one clock width on the same,
indicating the release of the bus back to 8086.
Queue Status – QS1, QS0
• The processor provides the status of the
queue on these lines.

• The QS signals can be used by external device

to find the internal status of the queue.
• The lock output is used to lock peripherals off
the system.

• This pin is activated by using LOCK: prefix on

any instruction.