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A C
B
D
•Every node has capacitance and
interconnects have resistance. It takes
time to charge these capacitances.
•Thus, output of all circuits, including
logic gates is delayed from input.
•For example we will define the unit
gate delay
EECS 42 Spring 2001 Lecture 19 Copyright Regents of University of California W. G. Oldham
A
C
B
Logic State
0 t
0
1 Output
0 t
0 D
EECS 42 Spring 2001 Lecture 19 Copyright Regents of University of California W. G. Oldham
A
C
B
Logic State
Input A
1
Input B
0 t
0
1 Output
0 t
0 D
EECS 42 Spring 2001 Lecture 19 Copyright Regents of University of California W. G. Oldham
Thus in the modified gate, C will be valid precisely one gate delay (D) after
the clock input CK, goes high (A and B are evaluated precisely when CK goes
high, what they do before or after this is irrelevant; CK must go low, then high
again before the NAND gate again looks at A and B).
EECS 42 Spring 2001 Lecture 19 Copyright Regents of University of California W. G. Oldham
A
B
D
C
Inputs have different delays, but we
ascribe a single worst-case delay
D to every gate
How many “gate delays for shortest path? ANSWER : 2
How many gate delays for longest path? ANSWER : 3
Which path is the important one? ANSWER : LONGEST
EECS 42 Spring 2001 Lecture 19 Copyright Regents of University of California W. G. Oldham
TIMING DIAGRAMS
Show transitions of variables vs time
A Logic state
B D A, B, C
t
C 0 B
Note B becomes valid one gate
delay after B switches D t
__
__ ( B C )
Note that ( B C )becomes valid two t
gate delays after B&C switch, because D 2 D
the invert function takes one delay and ( A B)
the NAND function a second. D t
D
No change at t = 3 D t
D 2D3D
EECS 42 Spring 2001 Lecture 19 Copyright Regents of University of California W. G. Oldham
Vin(t)
t
EECS 42 Spring 2001 Lecture 19 Copyright Regents of University of California W. G. Oldham
1.5
t
Vout(t)
Approximation
1.5
t
D D D
EECS 42 Spring 2001 Lecture 19 Copyright Regents of University of California W. G. Oldham
v IN ( t ) v OUT ( t )
The delay is mostly simply the charging of the capacitors at internal nodes.
We already know how to analyze this.
EECS 42 Spring 2001 Lecture 19 Copyright Regents of University of California W. G. Oldham
Example
The gate delay is simply the charging of the capacitors at
internal nodes.
Oversimplified example using “ideal inverter, II” v OUT ( t )
and 5V logic swing
5
v IN ( t ) v OUT ( t )
Vx
R MODEL
v IN ( t )
v IN ( t ) II v OUT ( t ) 2.5
RC = C
0.1ns 5
vIN vOUT
2.5 Vx
RC = 0.1ns so 0.069ns after vIN
switches by 5V, Vx moves 2.5V t
D = 0.069ns
EECS 42 Spring 2001 Lecture 19 Copyright Regents of University of California W. G. Oldham
Ideal v OUT ( t )
R VX Ideal
v IN ( t ) Logic Logic
gate gate
etc.
C
D = 0. 69 RC t
t
EECS 42 Spring 2001 Lecture 19 Copyright Regents of University of California W. G. Oldham
IF VIN is 2V then SN is
VIN =2V closed and SP is open.
+ Hence VOUT is zero (but
RN VOUT driven through resistance
- RN).
- SS = 0V
V
VDD = 2V
But if VIN is 0V then SP
RP is closed and SN is
VIN =0V open. Hence VOUT is
+
2V (but driven through
VOUT
resistance RP).
-
- SS = 0V
V
EECS 42 Spring 2001 Lecture 19 Copyright Regents of University of California W. G. Oldham
IF there is a capacitance at
VIN =2V the output node (there
+ always is) then VOUT
RN VOUT responds to a change in VIN
- with our usual exponential
- SS = 0V
V form.
VOUT
VDD = 2V
VIN jumps from
2V to 0V
RP
VIN =0V
+ VIN jumps from
VOUT 0V to 2V
- t
- SS = 0V
V
EECS 42 Spring 2001 Lecture 19 Copyright Regents of University of California W. G. Oldham
But now lets briefly review the energy used in charging and
discharging capacitances so we can start to estimate chip power.
EECS 42 Spring 2001 Lecture 19 Copyright Regents of University of California W. G. Oldham
R t=0
Capacitor initially uncharged
VDD C (Q=CVDD at end)
RD
Switch moves @ t=0
R t=0
P = (N) (CVDD2) (f )
In the last 5 years VDD has been lowered from 5V to about 1.5V. It
cannot go very much lower. But with clever design, we can
make a as low as 1 or 10%. That is we do not clock those parts
of the chip where there is no computation being made at the
moment.
Thus the 400W example becomes 4 to 40W, a manageable range
(4W with heat sink, 40W with heat sink plus fan on the chip).