Basic computer instructions

Instruction set completeness

 Timing and control
• All sequential circuits in the Basic Computer CPU are driven by a master clock, with
the exception of the INPR register.
• At each clock pulse, the control unit sends control signals to control inputs of the
bus, the registers, and the ALU.
• Control unit design and implementation can be done by two general methods:
– A hardwired control unit is designed from scratch using traditional digital logic
design techniques to produce a minimal, optimized circuit. In other words, the
control unit is like an ASIC (application-specific integrated circuit).
– A microprogrammed control unit is built from some sort of ROM. The desired
control signals are simply stored in the ROM, and retrieved in sequence to
drive the microoperations needed by a particular instruction.
Ex: SC has to provide timing signals T0, T1, T2, T3 and T4. at T4
SC is cleared if decode D3 is active then D3T4 : SC <- 0
An example register transfer:

T0 : AR <- PC

AT T0 THE CONTENTS OF PC ARE TRANSFERRED

TO AR
 Instruction cycle
• Fetch an Instruction from memory
• Decode the instruction
• Read the effective address from memory if the
instruction has an indirect address
• Execute the instruction
Fetch and Decode

• PC is loaded with the address of first instruction

• SC is cleared to 0
• Provides timing signals T0, T1, T2……..
• Micro operations for fetch and decode phases can be specified by
following register transfer statements
T0: AR <- PC
T1: IR <- M[AR], PC <- PC+1
T2: D0…… D7 <- decode IR (12-14), AR <- IR(0-11) I <- IR(15)
To provide data path for transfer of
PC to AR we must apply T0
- Place the content of PC onto bus
by making selection inputs
S2S1S0=010
- Transfer the content of bus to AR
by enabling LD input of AR
It is necessary to use timing signal
T1 to provide the following
connections to the bus system
• Enable read input of memory
• Place contents of memory on to
bus with S2S1S0=111
• Transfer contents of bus to IR by
enabling LD of IR
• Increment PC by enabling INR of
PC
Instruction cycle
Register Reference Instructions:
Memory Reference instructions
•
Input-Output and Interrupt
Input-output configuration
Input-Output instructions
Program Interrupt

• The computer may initiate information transfer by keep on

checking the flag bit to be set. This process of
communication is referred to as programmed control
transfer
• An alternative is letting external device inform the
computer when it is ready to transfer. In the meantime
computer may be busy with other tasks. This type of
transfer uses interrupt facility.
• Interrupt enable flip-flop IEN can be set and cleared
using ION and IOF.

• These two instructions provided to make a decision

as to whether or not to use the interrupt facility.
Demonstration of interrupt cycle