Chapter 3: Noise Sources

Massoud Pedram
Dept. of EE
University of Southern California
 Outline
 Background
 Noise in Digital Systems
 Capacitive Crosstalk
 Inductance Effects
 Ground Bounce
 IR Drop
 Skin Effect
 Electromigration
 EMI

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 On and Off Chip Clock Frequencies

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 Sources of Noise

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 Noise in Digital Systems
 Noise  Crosstalk
 Signals may be corrupted due  One signal interfering with
to many factors: another signal
 Power supply noise  Capacitive cross talk
 Crosstalk between RC lines on a chip
 Inter-symbol interference  Floating
 Real noise (thermal and shot)  Driven
Parameter variation

 Coupling between LC
 Independent random variables transmission lines
 Power supply noise  Near end

 Inductance and resistance of  Far end

supply network cause voltage
drops
 Spatial variation in the power
distribution network
 Temporal variation in the
power supply voltage

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 Noise Sources

VN  K NVs  VNI
 The first component represents those noise sources that are proportional to signal
amplitude e.g., crosstalk and signal-induced power supply noise
 The second component represents noise sources that are independent of signal
amplitude e.g., transmitter and receiver offsets and unrelated power supply noise
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 Proportional and Independent Noise
Sources
 Some of the noise sources
are proportional to signal
swing
 If you increase the signal
swing, you increase the noise
 Crosstalk
 Inter-symbol interference
 Signal return ratio (Zr/Z0)
 Signal-induced power supply
noise
 Need to cancel these sources
 Some noise is independent
of the signal swing
 Receiver or transmitter
sensitivity
 Receiver or Transmitter
offsets
 Independent power supply
noise
Reference offsets


of noise, not to overpower

them

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 Power Supply Noise
 The power supply network
has parasitic elements
 On-chip : resistive
 Off-chip: inductive
 Current draw across these
elements induces a noise
voltage
I
 RI  L
t
 Instantaneous current is
what matters
 Can be many times larger
than the DC current
 10W chip draws 4A at 2.5V
 Peak current maybe 10-20A

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 High Speed Challenges
 Signal quality of a single net: reflections and
distortions from impedance discontinuities in
the signal or return paths
 Crosstalk between multiple nets: with
ideal return paths

 Rail collapse in the power and ground

distribution network

 EMI from a component or the system

All signal integrity problems can be divided

into four categories. Each one has specific
causes. By identifying the causes of each
family of problems,design and technology
based solutions may be developed and
employed.
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 Three Levels of Analysis
 Rules of thumb: Feed your intuition, Self inductance 
useful for order of magnitude estimation 110nH/m

 First order approximations: Analytical

approximations, useful for quick estimates
and early design tradeoffs

 Numerical simulations: Field solutions,

requires parasitic extraction, SPICE, or
IBIS simulations

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 Don'ts and Do’s …
 Don’ts:
 Base a final design on a rule of thumb estimate or even an
analytical approximation
 Use rules of thumb and analytical approximations that are
inconsistent or lack fidelity
 Automatically and immediately reach for a field solver in
every case
 Do’s:
 Know your rules of thumb
 Know where to locate a range of analytical approximations,
each representing a non-dominated tradeoff point in terms of
accuracy and efficiency
 Check rule of thumb, analytical expression and field
simulation for acceptable consistency and high fidelity
 Use a field solver where and when absolute accuracy is
important

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 Maxwell’s Equations

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Capacitive Crosstalk
 What Is Crosstalk
 Crosstalk is a disturbance caused by the electric or
magnetic fields of some signal affecting another
signal in an adjacent circuit
 In an telephone circuit, crosstalk can result in your
hearing part of a voice conversation from another
circuit.
 The phenomenon that causes crosstalk is called
electromagnetic interference (EMI). It can occur in
microcircuits within computers and audio equipment
as well as within network circuits

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 Capacitive Crosstalk to a Floating Line
 Capacitive coupling between
on-chip lines
 Coupling over shared signal
returns K2C 
2Cc
2Cc  Co

 On-chip wires have significant

capacitance to adjacent wires
 On the same layer

 On adjacent layers

 When two driven adjacent signals b

and c change, a voltage is induced
on a “floating” middle line a:
 Capacitive voltage divider:

 Signal is not restored

Cc
KC  Va  KC (Vb  Vc)
Cc  Co
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 Capacitive Coupling to a Driven Line

 A simplified circuit model of two driven capacitively coupled lines.

Note that the aggressor makes an instantaneous transition (step
input). Vxtalk(t) gives the coupled voltage waveform on the victim line
2 and that line 2 is not changing itself.
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 Coupling to a Driven Line (Cont’d)
 If a victim line a is driven while an
aggressor line b changes, then a will be
disturbed but its steady state value will
be restored with a time constant of t =
R(Cc+Co)
 If the signal rise time tr of line b is slow
compared to t, then the magnitude of
disturbance on line a will be reduced
 The peak magnitude of voltage on line a
in response to a unit magnitude signal
on line b with rise time of tr is given by:
Cc t   t 
 1  exp   r  
Cc  Co  tr   t 

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 Miller Effect and Wire Delays
 Capacitive crosstalk can affect the RC delay of signals
propagating down the line
 If aggressor(s) switch in opposite direction of the victim, then
the effective capacitance is double the coupling capacitance
(due to the “Miller effect”) i.e., Ceff = 2Cc
 If aggressor(s) switch in the same direction, the effective
capacitance becomes zero (capacitive crosstalk is eliminated)
i.e., Ceff=0
 This can result in a large variation in the wire propagation
delay
 It is also a major cause of timing noise (skew and jitter) in
VLSI circuits

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 Parallel Striplines

 0.18m CMOS technology

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 Devgan’s Metric
Aggressor

Ramp input
voltage source

Victim

 Devgan’s metric states that:


Cij
Vn  V par (n)  Rn
tr , net ( j )
idesc(n)
jadj (i)
 It determines an upper bound on the peak node voltage in the victim line in
terms of:
 Coupling capacitance, Cij
 Interconnect resistance (plus source resistance, if present) of the victim net, Rn
 Rise time of at the output of the aggressor net driver, tr,net
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 Example Calculation of Devgan’s Metric
Agb

N2
Aga
N1
N0
Agc

N3

R2 N2

R1 C2b
N0 N1
tr , net (b)
R3 N3
C1a
R0=Rs
tr , net (a) C3c
tr , net (c)

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 Example of Devgan’s metric (cont’d)
R2 N2

R1 C2b
N0 N1
tr , net (b)
R3 N3
C1a
R0=Rs
tr , net (a) C3c
tr , net (c)

 Noise voltage at nodes N1, N2, and N3 are:

 C C2b C3c 
V1  ( R1  R0 )  1a   
 tr , net (a) tr , net (b) tr , net (c) 
 
C2b C3c
V2  V1  R2 ; V3  V1  R3
tr , net (b) tr , net (c)

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 Matrix Equations for Devgan’s Metric

 v1 is a vector of node voltages on the aggressor net

 v2 is a vector of node voltages on the victim net
 vs is the input to the aggressor net
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 Matrix Equations (Cont’d)

 Zeros in the conductance matrix indicate the fact that there is no

resistive path between net 1 and net 2
 The zero in the voltage source coefficient vector is due to the fact that
the excitation is applied only to net 1 and net 2 is connected to ground
 The matrix system can be rewritten in the Laplace domain as follows:

 Note that the diagonal entries of capacitance matrices C1 and C2

correspond to coupling capacitances
 Diagonal entries of the matrix Cc have a positive value

where

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 Matrix Equations (Cont’d)

 Above equation may be solved by applying an excitation of B1k to the

aggressor net 1 while open-circuiting all capacitances connected to it
 This implies that for an RC aggressor line with no path to ground, the
value of at all nodes

 Considering the circuit interpretation of in each

coupling capacitance can be replaced by a source of value k times the
coupling capacitance at the node; any capacitance to ground is removed.
Let us represent this vector of current sources be Ic
 Then the equation would be
 Then the value of V2,max can be obtained by solving net 2 with the above
transformation on all capacitances. This may be carried out by means of
a tree traversal

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 Pros/Cons of Devgan’s Metric


CT Lij
Vn  V par (n)  Rn
tr , net ( j ) Sij
idesc(n)
jadj (i)

 Lij is the length of adjacency between i and j , Sij is the separation

between the two, and CT is a proportionality constant determined by
the technology

 Advantages
 Convex and separable in Sij
 The optimal spacing problem (OSP) becomes a convex and separable
mathematical program
 Disadvantages
 No self capacitance or aggressor net resistance
 Unbounded behavior for decreasing rise time and/or increasing coupling
length

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 Vittal’s Approach
 Gives a generalization of the Devgan’s metric
 Accounts for the self capacitance and
resistance of the aggressor net
 No unbounded behavior
 Replaces the “driver rise time of the aggressor net”
with an “effective rise time of the aggressor net as
seen by the victim net” as follows:
tr , net ( j )
tr , net ( j ), net (n)   Dnet ( j )  Dnet (n)
2

 Total Elmore delay for the aggressor net, Dj

 Total Elmore delay for the victim net, Dn

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 Vittal’s Metric


CT Lij
Vn  V par (n)  Rn
tr , net ( j ), net (n) Sij
idesc(n)
jadj (i )

 The effective rise time of the aggressor net, net(j), as

seen by the victim net, net(n), is then a function of ALL
spacing variables. Therefore, it is
 Non-separable
 Non-convex in general
 OSP becomes very compute-intensive

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 Kuhlmann’s approach

 Waveform 1 shows the final value theorem method (Devgan’s metric)

 Waveform 2 shows the real noise signal used in Kuhlmann’s approach

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 Kuhlmann’s approach (cont’d)
 Model the input voltage of the aggressor as an exponential function

where p corresponds to the time constant of the driver of the aggressor

 For computational efficiency, we use the following approximation for the
noise voltage induced on the victim net:
s

 Using AWE, the coefficients of V2(s) can be found according to following

equations:

 Next we use V2(t) in the noise matrix equations which shows better results
than the Devgan’s metric
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 Capacitive Crosstalk Countermeasures
 Routing rules should be put in place to limit the
magnitude of the capacitive crosstalk between any
pair of signals
 Floating signals should be avoided, and keeper
devices should be placed on dynamic signals to
reduce susceptibility to cross talk
 Signal rise time should be made as long as possible,
subject to timing constraints, to minimize effect of
crosstalk on driven nodes
 Sensitive signals should be separated from full swing
signals or even shielded by conductors on either side
that are tied to power or ground

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 Coupled Transmission Lines

 Circuit schematic of N on-

chip interconnects

 Circuit schematic of N on-

chip interconnects that are
electromagnetically coupled
(may ignore the L values for
now)

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 Crosstalk between Transmission Lines
 A signal transition on one
transmission line induces forward
and reverse traveling waves on
adjacent transmission lines

 Consider the scenario:

dx

tx=dx/n tx
 Near-end crosstalk:
VC ( x, t )  krx VA ( x, t )  VA ( x, t  2t x )

 Far-end crosstalk:
VA ( x, t )
VD ( x, t )  k fxt x
t
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 Crosstalk (Cont’d)
 Inductive and capacitive
coupling add at the near end of
the line
 Both waves are positive
 Pulse begins at beginning of
coupled section
 Inductive and capacitive
coupling subtract at the far end
of the line
 In a homogeneous medium
cancellation is exact
 Narrow pulse coincident with
wave on aggressor
 Reverse and forward coupling coefficients:
k  klx k  klx
krx  cx k fx  cx
4 2

Cc M
kcx  ; klx 
Cc  Co L
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 TX Line Crosstalk Countermeasures
 High swing signals should not be routed on
lines immediately adjacent to low swing or
other sensitive signals
 The capacitive and inductive coupling
coefficients should be matched to eliminate
forward (far-end) crosstalk
 Place all signal lines between a pair of return
planes
 If the forward coupling coefficient is nonzero,
avoid long parallel runs of transmission lines
 When possible, both ends of all transmission
lines should be terminated in the characteristic
impedance of the line

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 Countermeasures (Cont’d)
 Signal rise times should be made as long as possible
subject to timing constraints
 This reduces far-end crosstalk, which is directly proportional
to the signal derivative and this is reduced directly as the
derivative is reduced
 Near-end crosstalk is proportional to the maximum difference
in the signal level across the coupled length and thus is
reduced proportionally once the rise time is greater than tx,
the coupled time
 Signals on adjacent layers should be routed in
perpendicular directions
 This results in zero inductive coupling and negligible
capacitance coupling
 The two lines of a differential pair should be spaced
close together and far from the lines of other pairs to
keep the fields local to the pair

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Inductance Effects
 Introduction
 On-chip inductance effects have become increasingly significant
because:
 For performance considerations, some global signal and clock wires are
routed with large widths and thickness at the top levels of the metal to
minimize delays. This decreases the resistance of the wires, making their
inductive impedance comparable to the resistive part.
Z  R  jL
 As the clock frequency increases and the rise times decrease, electrical
signals comprise more and more high-frequency components, making the
inductance effects more significant.
 With the increase of chip size, it is fairly typical hat many wires are long and
run in parallel, which increases the inductive cross talk and delay.
 With the push of performance, some low-resistively metals,e.g. Cu wires,
have been explored to replace Al in order to minimize wire RC delays. This
could make the wire inductive reactance larger than the resistance.
 Examples of Inductance effect
 Overshoot/undershoot edges
 Ldi/dt voltage drop
 Long range cross talk
 Frequency dependent resistance

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 Adverse Effects of the Inductance
 Signal quality
 Inductive discontinuity and ringing
 Ground bounce
 Collapse of the power and ground rail voltage
 Crosstalk
 Distributed mutual inductance in uniform
transmission lines and lumped mutual inductance
(SSO)
 Electromagnetic interference (EMI)
 Generation of common mode noise currents

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 Clock Frequency vs. Equivalent Inductance

 At 1 watt
power
dissipation, to
achieve 100
MHz clock
requires an
equivalent lead
inductance on
the order of
half a nH

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 What Affects the Magnetic Field Lines
 Magnetic field lines exist around
all current carrying conductors

 The number of field lines depends on:

 Current in the wire
 Proximity of the return path
 Cross section of the wire
 Other nearby currents
 Material that the wire is composed of
 Proximity of nearby metal surfaces
 Dielectric material surrounding the wire  The magnetic field line
density drops off with
distance

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 Types of Inductance
 Inductances may be classified as:
 Self inductance
 Mutual inductance
 Or they may be classified as:
 Partial Inductance
 Loop inductance
 Loop self inductance
 Loop Mutual inductance
 Effective (or total) inductance

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 Self and Mutual Inductances
 Inductance is related to the number of field lines around the
conductor per ampere of current
 Different types of inductance:
 Self or mutual
 Loop or partial
 Effective (total)

 Self inductance
 # of field lines/amp of its own current
 Mutual inductance
 # of field lines/amp of another line’s current

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 First-order Equation for Self Inductance
Radius=r

m0 d   2 d  3
Lself   ln    
2   r  4
b

m d   2 d  1
Lself  0  ln    ln( )  
2   bc  2

 Note that  is obtained from lookup table. For more information visit:
http://home.san.rr.com/bushnell/self_inductance.htm
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 First-order Equation for Mutual Inductance

Radius=r

m d   2d  
s d Lmutual  0 ln  
2   s  

 2
m d   2d  s  s  
sd Lmutual  0 ln   1    
2   s  d  2d  


 Notice the change in mutual inductance with rod separation

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 Voltage Across the Inductance

V
 When the number of field lines around a conductor changes,
a voltage is induced:
N (LI ) I dI
V  L L
t t t dt

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 Partial Inductance
Inductance of
this part

Wire a La

LM
Wire b (return path)
Lb

 Partial inductance is the portion of loop inductance for a

wire segment when its current returns via the infinity
 Any loop can be divided into segments
 Every segment has a partial self inductance, which denotes the
number of field lines around the segment, when the only
current is through this section
 Every segment has a partial mutual inductance to every other
segment, which denotes the number of field lines around both
segments, when current goes through only one section
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 Properties of Partial Inductance
 Partial self and mutual inductance are based on
geometry only
 They may be obtained by using a 2D/3D field solver
such as Avanti’s Raphael or MIT’s FastHenry
 The return path or the current loop may be
determined through spice simulations
 The partial self and mutual inductances may be
frequency and proximity dependent

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 Loop Self Inductance
 The loop inductance accounts for the presence of the return
path current

Total number of field lines around b

 Loop self inductance of coil b =
current in b

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 First-order Equation for Loop Self
Inductance
signal Radius=r

s Two parallel rods

return

d
m0 d s
Lloop, self  ln( )
 r
d

Two parallel planes

s
Lloop, self  m0 d
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w
 Loop Mutual Inductance

 Loop self inductance of coil b = # of field lines per

ampere around b, which are due to the current in b
 Loop mutual inductance of a and b = # of field lines per
ampere around a, which are due to the current in b

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 First-order Equation for Loop Mutual
Inductance

a
b
h

m0 a 2b 2
Lloop, mutual  
2 3/ 2
 a 2  h2 
 
 
 For more information visit:
http://www.physics.uq.edu.au/people/ficek/ph348/sols/sol4/node4.html

M. Pedram
 Induced Voltages due to a Fixed dI/dt
D

self dI a
R Va, noise  Lself 
dt
a

a
mutual dIb
Va, noise  Lmutual 
b
dt

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 Effective Inductance
 Effective (a.k.a. total or net) inductance is the total
number of field lines per ampere of current which are
around a section of a loop
Wire a La

LM
Wire b (return path)
Lb

 The effective inductance of wire “b” is:

Leff ,b  Lb  LM
 Effective inductance
 Depends strongly on where the signal path is
 Increases (decreases) if the return path is moved away from
(brought closer to) the signal path
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 Effective Loop Inductance
Wire a La

LM
Wire b(return path)
Lb

Leff  Leff , a  Leff ,b

 La  LM  Lb  LM  La  Lb  2 LM

 Loop inductance increases as wires are moved farther

from one another
 Some key questions are:
 What happens to characteristic impedance as wires are moved
closer together?
 What is the voltage drop across the whole loop for a fixed dI/dt?
 What design features influence Lloop ?
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 Signal Risetime and Ringing Effect
 Inductance is the number of field lines per ampere of current
 0.8mm wide or narrower wires do not have significant
inductance effects

 The worst case inductance is when all aggressors switch in the

same direction
 In general, with the inductance effect, signal rises faster. The
most serious inductance impact is high-Q ringing where
 
L/C   
Q Overshoot  exp  
R  Rs  4Q 2  1 
 
 Rise times shorter than one-half 2 LC cause the worst ringing
 The inductive cross talk noise tops off at lengths of around
4000m to 6000m length

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Ground Bounce
 Ground Bounce
 Digital logic requires a stable, quiet, DC supply voltage while drawing a
large AC current with very high-frequency components comparable to
signal rise times (about 200A from power supply and derivative at the
point of use over 200GA/s)
 The supply and ground are distributed over a network with inductive
and resistive components
 The current causes IR drop across the resistive component
 The derivative of current causes Ldi/dt across the inductive components

A Typical Power Supply Network

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 The Power Distribution Problem
 Modern digital systems operate at small DC voltages
 1.5 to 3.3V
 must be held to within ±10% (or less)
 and draw large AC currents
 10A or more per chip, 100A per board, KA in a system
 May go from 0 to full current in less than one clock cycle
 over a supply network with parasitic elements
 Inductance of bus bars, PC boards, packages, and bond wires
 Resistance of on-chip wires

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 Example of Ground Bounce Effect

A simplified circuit schematic of 16 output buffers switching

simultaneously

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 Other Names for Ground Bounce
 Other names are:
 I noise
 Switching noise
 dI/dt noise
 SSO (simultaneous switching output) noise
 SSN (simultaneous switching noise)

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 A Typical Power Supply Network

 Actually a tree with branching at each level

 Parasitic inductance (off-chip) and resistance (on-chip)
 Power and ground networks are usually symmetric
 Capacitance added to give a tapered frequency response

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 Typical Load Current
 For a given clock domain, load is usually periodic with the clock
 May stop or start in a single cycle
 With multiple clock domains, they may drift into phase
reinforcing one another
 Load is often resistive, varying linearly with supply voltage
 Some loads are high impedance, constant independent of supply
voltage

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 Local Loads and Signal Loads
 Local loads pass current from a
point in the local power network
to one in the local ground network
 Current can be supplied from a
nearby bypass capacitor
 Signal loads connect a point in the
power network via a signal lead to
a distant point in the ground
network
 Usually due to unbalanced signaling
 Current must return over a long path
 Bypass capacitors are not effective

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 Inductive (Off-chip) Power Supply
Noise
 Each section of the supply network is an LC circuit
1/ 2
 Has a resonant (natural) frequency,    LC 
LC
 Inductor carries DC current (  LC)
 Capacitor supplies AC current (  LC)
 At LC, the LC impedance is infinite, thus, a small current
will cause large voltage oscillations
 Size the bypass capacitor to
 Supply cycle to cycle AC current with acceptable ripple
 Handle inductor start/stop transient

M. Pedram
 Response of an LC Section to Typical
Supply Current

 Over a clock
cycle,
inductor
current is
essentially
constant, Iavg ;
Load current
varies
considerably;
Capacitor
current is the
difference
between the
two;
Capacitor
voltage
ripples due to
this AC
current

M. Pedram
 Bypass Capacitor to Handle Normal Load
in a Cycle

 Inductor carries the average (DC)

current and the bypass cap. supplies
the instantaneous (AC) current while
keeping supply variation less than
some threshold V
 ki reflects the maximum fraction of
total charge transferred each cycle, t
Qck, that must be supplied by the
capacitor at a given instant, t ki  max

0
( I  I avg )dt

 ki is a function of the waveform and tavg tck

varies from a max of 1 for a delta
function to 0.25 for a triangle
waveform to 0 for a DC current Typical
value is 0.25 to 0.5
M. Pedram
 Bypass Capacitor to Handle Start/Stop
Transient
 When circuit is off, inductor
current is 0
 During startup, the capacitor
must supply current to the load
while the inductor current ramps
up
 Similarly, when the circuit shuts
down, the capacitor must absorb
the inductor current while it
ramps down
 In either case, the situation is
that of a step current into an LC B
circuit
 Response is a sine-wave
 Vmax is the threshold for supply B
variation

max
M. Pedram
 Putting It Together: Sizing the Bypass
Capacitor

 Bypass capacitor must be sized

to handle both types of inductive
power supply noise
 ripple due to non-uniform current
within a clock cycle
 start/stop transients
 maximum ripple can happen at peak
or trough of transient i.e.

 Approximate capacitance
requirement by summing the
independent requirements

M. Pedram
 The Truth about Bypass Capacitors
 Most capacitors are only capacitors
at low frequencies
 Capacitors have parasitic series
resistance and inductance
 Every pico-farad has its very own
nano-Henry
 Two key breakpoints
 LC frequency
 RC frequency
 Capacitors are ineffective at
bypassing currents above either of
these frequencies

M. Pedram
 Impedance vs. Frequency for Typical
Capacitors

M. Pedram
 Controlling the Ground Bounce
Wire a La

LM
Wire b(return path)
Lb

 Ground bounce
dIb dI
Vb  Leff ,b  ( Lb  LM ) b
dt dt

 Minimizing the ground bounce:

 Minimize dI/dt: don’t use shared return path (instead use
multiple return paths)
 Low Lb: use wide return path conductor (use planes, short
length)
 High LM: put the signal close to its return path -- 50ohm signal
M. Pedram
lines, low Z0 power/ground planes
 Signal Path Topologies for Low Bounce
 The following geometries have the lowest total
inductance of the current return paths:
 Coaxial cable (which is not very practical)
 Wide, closely spaced planes (too low a Z0)
 Strip line
 Micro strip
 Twin lead  Keep Zpower supply < 5% Zload

 The golden rule in designing the power and ground

distribution network is to keep the impedance looking
into the power supply << Zload
M. Pedram
 Summary of Ground Bounce
 Ground bounce
 Is the voltage drop across the return path
 Can be caused by signal-returns or power-returns
 Is minimized by controlling the total inductance of the return
path
 Is strongly dependent on partial self inductance between
signal and return path
 Is strongly dependent on partial mutual inductance between
signal and return paths
 Primarily arises in packages and connectors
 Anything (such as gaps in planes) that increases the total
inductance of the return path increases the ground bounce
 Also drives common currents into the cables and creates EMI

M. Pedram
IR Drop
 Power Distribution Trends
 The on-chip power distribution problem is
getting much harder as technology evolves
 Combination of
 lower voltages
 higher current density
 thinner metal layers
 larger chips
 We are quickly approaching the point where
peripheral bonding will not be adequate for
high-performance chips

M. Pedram
 Logic Current Profile
 Why does on-chip logic produce a ‘ spikey’ current profile?
 Consider the logic that generates the current
 Current is drawn to charge gate and wire capacitance Q=CV,
E=0.5 CV2
 Typical behavior includes
 circuit idle before clock edge
 very little current
 exponential clock amplification just before clock edge
 exponential ramp up in current
 flip-flops are clocked
 current depends on activity factor
 Fanout in a logic circuit
 exponential ramp up in current
 Fan-in or selection in a logic circuit
 drop in current

M. Pedram
 Logic Current Profile Examples (Con’t)
 A memory or register array
 fanout in decoder
 selection of word-line
 amplification in S/A
 selection in multiplexer
 A carry-lookahead adder
 modest fan-out in PGK blocks
 fan-out in carry tree
 fan-in in carry tree, but with amplification
 amplification to drive output
 Control logic
 much like the decoder
 fan-out in the first few stages
 then tree fanning in to flip-flops
 often a long, serial tail
 Overall current profile is the superposition of all of these profiles

M. Pedram
 Worst-Case vs. Average Logic Current
Profile
 Current drawn is often very data dependent
 e.g., a data path may switch 64-bits from all 0s to
all 1s
 on average only 1/4 of the bits will have this
transition
 when there is a transition at all
 For noise analysis we must consider worst-
case power
 cannot allow possible, but unlikely events to cause
system failure
 For battery life we may consider average
power

M. Pedram
 IR Drops
 Power distribution network is designed to keep IR drop on VDD
and GND networks within limits
 e.g., for 10% supply variation, can drop at most 5% on each supply
 Networks are usually designed specifically for the loads of a
given chip. However, we can gain insight into the process by
considering a uniform load
 For example, suppose current densities are
 – J peak = 0.3A/mm 2
 – J avg = 0.05A/mm 2
 For a peripheral bonded chip, VDD and GND are usually
distributed by combs with interdigitated fingers
 – a hierarchy of such combs is often used
 How much of a metal layer (or how many layers) do we need to
distribute this power?

M. Pedram
 Power Distribution Network: The Top-level
View

GND

VDD

M. Pedram
 Calculation of the IR Drop

 A simplified equivalent circuit of one half of a pair of power buses is shown in

the above figure; Power and GND are supplied from the left side of the figure
 The buses are then divided into N segments, each with resistance:
L p rw
Rp 
2 NW p
 Lp is the total length of the global power buses; rw is the sheet resistance of
the wire, and Wp is the width of the global power buses
 The current source associated with each segment supplies power to circuits
in an area of: L pW p
Ap 
2N k p
 kp is the fraction of the metal layer devoted to the power buses of one
polarity
M. Pedram
 IR Drop Calculation (Cont’d)
 Voltage integrates along the strip, therefore, the IR drop from
the edge to the center of the two buses in a square shape chip
is: N /2 N /2

 
2 i J pk L p rw
VIR  i J pk Ap R p 
4N 2k p
i 1 i 1

 Jpk is the peak current density

 If N goes to infinity, the above equation can be written as:

Lp / 2 J J pk rw L p 2

pk rw x
VIR  dx 
0 kp 8k p

M. Pedram
 IR Drop Countermeasures
 Use an area-bonded chip so that power
need not be distributed from the chip edge
 Use more or thicker metal layers to
distribute the power to reduce the
effective resistivity, rw
 Use on-chip bypass capacitors to flatten
the current profile so the distribution need
only be sized for average rather than the
peak current

M. Pedram
Skin Effect
 Transmission Line Loss Models
 Losses that remain constant with
frequency can be modeled as:
 Dielectric constant

 Dissipation factor, tan(d)

 RDC

 Other losses, RAC, are proportional to

frequency  f

M. Pedram
 Signal Propagation in the Frequency
Domain

 When a sine wave is launched into a transmission line, the frequency of

the sine wave propagates unchanged, but the amplitude will drop off. As
it propagates, the amplitude will be exponentially attenuated. This can
be described with an attenuation per length coefficient, with the units of
dB per inch, for example
M. Pedram
 Modeling Lossy Lines in the
Frequency Domain

 In general, we will be assuming that R and G may be frequency

dependent, but C and L will be constant in frequency, and will
use the high frequency limits for these terms. As we shall see,
frequency dependence of inductance can be accounted for in the
resistance term

M. Pedram
 Low Loss Approximation
 At low frequencies (towards the DC end), current is uniformly
distributed over the cross section of each conductor. We will refer to
these frequencies as the low-frequency region
 As the frequency increases, due to the induced electric field, the
current distribution starts changing. There are three reasons :
 Edge effect: the current tends to concentrate at the sharp edges of a
conductor which affects both the signal conductor and the ground
conductor
 Proximity effect: particularly pronounced on the ground conductor, the
current of which tends to concentrate below the signal conductor as the
frequency increases
 Skin effect: pronounced in the high-frequency region on both conductors,
where the current becomes concentrated in the thin layer at the surface

Microstrip
Stripline

M. Pedram
 Skin Effect
 The tendency of alternating current to flow near the surface of a
conductor, thereby restricting the current to a small part of the
total cross-sectional area and increasing the resistance to the flow
of current
 High frequency current flows primarily on the surface of a
conductor with current density falling off exponentially with
depth into the conductor:
 d
J  exp   
 d
 The skin depth, d, the depth where the current has fallen off to
exp(-1) of its normal value is given by:
1/ 2
d   f m 

 1/ is the conductivity of the material, and f is the frequency of

the signal

M. Pedram
 The Origin of Skin Depth

 At DC, if each ring has the same current, which one has more
inductance?
 At high frequency, which ring has more impedance?
 If you were an electron, where would you want to be?
 The center path has the highest inductance since it has all the field lines
of the outer ring plus the field lines that are between it and the outer
ring. In general, the self inductance of the current path will decrease as
you approach the outer edge

M. Pedram
 Skin Depth Limited Current Distributions

M. Pedram
 A Simple Approximation
Assume the signal path width is w and its thickness is t

M. Pedram
 Resistance Modeling

Recall that f is in MHz

M. Pedram
 Inductance is Frequency Dependent

M. Pedram
 Electromigration and
Electromagnetic Interface
 Electromigration
 Over long distances, current density must be kept low to avoid large IR
drops; Over short distances, current density must still be kept low to
avoid metal migration
 Over time, wires that carry high current densities will fail as the metal is
eroded away
 think of your wire as a fuse
 Migration threshold varies depending on process, temperature, and
lifetime
 If a metal layer is subjected to an average current density of greater
than about 1mA/mm2 (109 A/m2), the layer will slowly fail
 This is often a factor on short power buses that connect from the main
bus to a point of high current use
 To avoid metal migration the fraction kp of metal devoted to each
power bus must satisfy: 3
10 J aw Lp
kp 
2t
 where t is the thickness of the metal layer, Jaw is in A/mm2
 It can also be a factor on the output of high-current drivers
 Migration applies to vias as well as wires

M. Pedram
 Electromagnetic Interference (EMI)
 Large external electric and magnetic fields can couple into circuit nodes
and cause noise
 For both types of fields, susceptibility is reduced by keeping a minimum
distance between a signal and its return
 For E fields, the induced voltage is proportional to the distance between
the signal and return path
 For B fields , the amount of flux coupled is proportional to the area of
the loop between the signal and the return path
 Electromagnetic Interference is rarely a problem in digital circuits unless
they are operated near large sources of fields
 Usually, the larger concern is the interference created by the digital
system
 The same techniques that reduce susceptibility to external fields also
reduce emissions by the digital system
 Most digital systems can be made “quiet” naturally by keeping signals
and return paths close together, balancing currents in external cables,
controlling rise time on signals, and properly terminating lines
M. Pedram
 Appendix: How to Minimize Inductance
Effects
 Dedicated ground wires

Lloop  L11  L12  L21  L22

 Differential signals

Common mode noises such as inductive effects may be rejected

However, the design suffers from longer delays to Miller effect

M. Pedram
 How to Minimize Inductance Effects
(Cont’d)
 Buffer Insertion

Rl Ll Cl
, , ; k 1
 Splitting wires n kn / 2 n

G S S G G S G

G S S S S G G S S S S S S S S G

M. Pedram
 How to Minimize Inductance Effects
(Cont’d)
 Termination
Shunt-RC termination

Series_R Shunt-C termination

Series_R termination

Diode termination

 Continuous power/ground planes

 Continuous power/ground planes on-chip provides an impedance-
controlled low-loss signal lines

M. Pedram
 Appendix II:
Values for Single Supply Noise vs. Distance

M. Pedram
 On-chip Parasitic Capacitance

M. Pedram
 Typical Transmission Line Parameters
and Coupling Coefficients

M. Pedram