Beruflich Dokumente
Kultur Dokumente
• Introduction
• CMOS devices
• CMOS technology
• CMOS logic structures
• CMOS sequential circuits
• CMOS regular structures
organic polymer)
• The photoresist is exposed to ultra Mask
removed (development).
– The patterned photoresist will now
serve as an etching mask for the SiO2 Substrate
SiO2
Substrate Substrate
2. Photoresist coating 5. Polysilicon etching
photoresist
Substrate Substrate
3. Exposure UV light
6. Final polysilicon pattern
Substrate Substrate
CVD oxide
Poly gate Metal 1
S D
n+ n+ Wdrawn
Leffective
B
Gate oxide
p-substrate (bulk)
CVD oxide
Poly gate Metal 1
S D
p+ p+ Wdrawn
Leffective
B
Gate oxide
n-well (bulk) n-well
p-substrate
< 1mm
P+ -type wafer
n-well
n-well
p-type
n+ n+ n+ n+
p-substrate (bulk)
resit
n-well
p+ channel-stop implant
p-type
n-well
active area after LOCOS
p-type
Field oxide
XFOX
0.54 XFOX Silicon surface
0.46 XFOX
Silicon wafer
n-well
p-type
Gate oxide
tox tox
n-well
p-type
Polysilicon mask
Polysilicon gate
n-well
p-type
p+ implant (boron)
p+ mask
n-well
Photoresist
p-type
n-well
Photoresist
p-type
n-well
n+ p+
p-type
Contact mask
n-well
n+ p+
p-type
metal 1 mask
metal 1
n-well
n+ p+
p-type
metal 2
Via metal 1
n-well
n+ p+
p-type
Yield (%)
• Scribe cut and packaging
also contribute to the final 20
1.0 defects/cm2
yield
2.5 defects/cm2
• Yield can be approximated 5.0 defects/cm2
by: Y e AD 10
0 2 4 6 8 10
A - chip area (cm2) Chip edge ( area in mm)
p-well
n+ p+
n-type
p-well n-well
n+ epitaxial layer p+
n+ substrate
n+ p- n+ p+ n- p+
thinoxide
sapphire (insulator)
n+ poly p+ poly
Silicide Oxide spacer
n+ p-doping
n+ p+ n-doping
p+
n-well
Shallow-trench isolation
Source-drain
p-type substrate extension
• Device/die area:
W L (1/)2 = 0.49
– In practice, microprocessor die size grows about 25% per
technology generation! This is a result of added functionality.
• Transistor density:
(unit area) /(W L) 2 = 2.04
– In practice, memory density has been scaling as expected.
(not true for microprocessors…)