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Digital systems design

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Objectives

• Introduce students to advanced topics in

Digital System Design

– Synchronous Sequential Circuit Design using

State/ASM diagrams

– Hardware Description Languages

– EDA tools

– ASIC/FPGA implementation technologies

Outcomes

• Understand the digital system design flow

• Understand the role of EDA tools in ASIC/VLSI

design

• Be familiar with ASIC, PLD, FPGA technologies

• Design hazard-free synchronous and

asynchronous digital systems using ASM

• Implement Mealy and Moore ASMs using

PROMs, multiplexers, PLDs, FPLAs, FPGAs

• Become fluent in VHDL

• Understand Verification concepts and design

testbenches

Description

• Digital Systems Design - ASMs:

– ASMs, Mealy and Moore machines. ASM charts.

– State machine implementation using PROMs and

multiplexers.

– Finite state machine implementation using FPLAs.

– Timing. Glitch minimization techniques.

– Asynchronous input systems. Asynchronous input

synchronization

Description

• ASIC architectures and Implementation

Options

– Synthesis and EDA tools for ASIC and FPGA

implementation

– Semi-custom / full custom ASICs.

– Gate Array, Standard Cell, Full Custom,

CMOS/BI-CMOS technologies

– PLDs and FPGAs.

Description

• EDA Tools

– Synthesis

• VHDL Synthesis coding guidelines

• Synthesis optimization options

– Implementation

Textbooks and References

• J. F. Wakerly, Digital Design: Principles

and Practices, Prentice Hall, 2003.

• V. Pedroni, The student’s guide to

VHDL, Morgan Kaufmann, 1998.

• M. Mano, Digital Design, Prentice Hall,

2002.

• T. Floyd, Digital Fundamentals, Prentice

Hall, 2002.

Basic Logic Gates

Logic

A A A Function

A X X X X

B B B

Gate

X=A X=A B X =A+ B X=A+ B Symbol

A X A B X A B X A B X Logic

0 0 0 0 0 0 0 0 0 0 0 Expression

1 1 0 1 0 0 1 1 0 1 1

1 0 0 1 0 1 1 0 1

1 1 1 1 1 1 1 1 0 Truth

Table

Basic Logic Gates with Inverted Outputs

A A A

A X X X X

B B B

A X A B X A B X A B X

0 1 0 0 1 0 0 1 0 0 1

1 0 0 1 1 0 1 0 0 1 0

1 0 1 1 0 0 1 0 0

1 1 0 1 1 0 1 1 1

Revision on MSI Devices

Fundamentals (Chapter 5)

MSI Devices

• Medium Scale Integration (MSI) devices are

digital devices that are build using a few tens to

hundreds of logic gates.

packed in a single Integrated Circuit (IC), or as

building blocks for other, more complex devices

such as memory devices or microprocessors.

• Some typical MSI devices are the following:

– Encoders and Decoders

– Full Adders

Examples of MSI Devices

Decimal to BCD Encoder

DEC/BCD

4-to-1 Multiplexer

I3 1 2

D0 1 0 3

1 2 3 D1

I2

D2 1

D3 Y3

4 5 6 D4 Y2 I1

1

Y1 0

D5

Y0

7 8 9 D6

1

I0

4/1 Mux

D7

D8

0 D9

1 1 1 1 0 1 2 3 4 5 6 7 8 9

0 0 0 0

0 1 0 1 0 1 0 1

BCD/DEC

Y0

Y1

A0 Y2

Y3

A1 Y4

A2 Y5

A3 Y6

Y7

Y8

Y9

Decoders

• A decoder is a combinational digital circuit with a number of inputs ‘n’ and a number of

outputs ‘m’, where m= 2n

• Only one of the outputs is enabled at a time. The output enabled is the one specified by

the binary number formed at the inputs of the decoder.

• On the circuit below, the inputs of the decoder are connected on three switches,

forming the number 5 [(101)2], thus only the lamp #5 will be ON

1 1 1 0 1 2 3 4 5 6 7

0 0 0

0 1 0 1 0 1

3/8 DEC.

Y 0

Y 1

A 0

Y 2

A 1 Y 3

Y 4

A 2

Y 5

Y 6

Y 7

2 to 4 Line Decoder:

2-to-4 Line Decoder

2/4 DEC A 1 A 0 Y 0 Y 1 Y 2 Y 3 Y0 = A1 A 0 Y 0

Y 0 0 0 1 0 0 0 Y1 = A 1 A 0 A 1

A 1 Y 1

Y 1 0 1 0 1 0 0 Y2 = A1 A 0

A Y Y 2

0 2 1 0 0 0 1 0 Y3 = A1 A 0

A 0

Y 3 1 1 0 0 0 1 Logic Y 3

Expressions

Logic Symbol Truth Table Logic Circuit

2/4 DEC E A 1 A 0 Y 0 Y 1 Y 2 Y 3 Y 0 = E A1 A 0

A 1 Y 0

A 1 Y 0 0 X X 0 0 0 0

Y1 = E A 1 A 0

Y 1

A 0 Y 1 1 0 0 1 0 0 0

E

Y2 = E A 1 A 0

Y 2 1 0 1 0 1 0 0 Y 2

E Y 3 1 1 0 0 0 1 0 Y3 = E A 1 A 0 A 0

Y 3

1 1 1 0 0 0 1 Logic

Logic Symbol Truth Table Expressions Logic Circuit

3 to 8 Line Decoder:

3-to-8 Line Decoder with Enable Input

3/8 DEC E A 1 A 1 A 0 Y 0 Y 1 Y 2 Y 3 Y 4 Y 5 Y 6 Y 7 Y 0

Y 0 0 X X X 0 0 0 0 0 0 0 0

A 2 Y 1

Y 1 1 0 0 0 1 0 0 0 0 0 0 0

A 2 Y 2 Y 2

1 0 0 1 0 1 0 0 0 0 0 0

A 1 Y 3 1 0 1 0 0 0 1 0 0 0 0 0 Y 3

A 1

A 0 Y 4 1 0 1 1 0 0 0 1 0 0 0 0

Y 4

Y 5 1 1 0 0 0 0 0 0 1 0 0 0

Y 5

Y 6 1 1 0 1 0 0 0 0 0 1 0 0 A 0

E Y 7 1 1 1 0 0 0 0 0 0 0 1 0 Y 6

1 1 1 1 0 0 0 0 0 0 0 1

Y 7

E

Logic Symbol Truth Table Logic Circuit

Multiplexers

• A multiplexer is a device that has a number of data inputs “m”, and number of

control inputs “n” and one output, such that m=2n. The output has always the same

value as the data input specified by the binary number at the control inputs.

• The rotary switch (selector) shown in figure (a) below, is equivalent to a 4-to-1

multiplexer.

• The sliding switch shown in figure (b) below, is equivalent to an 8-to-1 multiplexer.

1 1 0 1 0 0 1 1

I3 1 2

1 0 3

I2 I0 I1 I2 I3 I4 I5 I6 I7

1

1

I1

0

Y 8/1 Mux

I0

1 4/1 Mux

0

Internal structure of a 2-to-1

multiplexer.

• The design of a 2-to-1 multiplexer is shown below.

• If S=0 then the output “Y” has the same value as the input “I0”

• If S=1 then the output “Y” has the same value as the input “I1”

2-to-1 Multiplexer

2/1 MUX S I1 I0 Y

I0

I0 0 0 0 0

Y I1 I0

I1 0 0 1 1 S 00 01 11 10 1/2 Dec.

S 0 1 0 0 0 0 1 1 0 S Y

Logic Symbol 0 1 1 1 1 0 0 1 1

1 0 0 0

S Y 1 0 1 0 I1

Y = S I 0 + S I1

0 I0 1 1 0 1

1 I1 1 1 1 1

Logic Expression Logic Circuit

Logic Function Truth Table

1-bit Full Adder

8/1 Mux

A B Cin Cout Sum A 0 I0

Sum

0 0 0 0 0 0 I1

0 0 1 0 1 B 0 I2

0 1 0 0 1 1 I3

Cin Y Cout

0 1 1 1 0 0 I4 4/1 Mux

Cout

1 0 0 0 1 1 I5 0 I0

1 0 1 1 0 1 I6 A I1

1-Bit Full Adder using gates Y Cout

1 1 0 1 0 1 I7 A I2

S2 S1 S0 1 I3

1 1 1 1 1

3/8 Dec. A S1 S0

A

Truth Table A Y0 B B

B B Y1 Cin

Cin

C Y2 S2 S1 S0

Cin

Y3 0 I0

S1 S0

A B Cin Y4 1 I1 A I0

Y5 1 I2 A' I1

1-Bit F.A. En Y Sum

Y6 0 I3 A' I2

Y Sum

Y7 1 I4 A I3

Cout Sum

0 I5 4/1 Mux

0 I6 1-Bit Full Adder using 4/1 multiplexers

Logic Symbol Cout Sum 1 I7

8/1 Mux

1-Bit Full Adder using a decoder 1-Bit Full Adder using 8/1 multiplexers

4-bit Full Adder (Ripple-Carry Adder)

• To obtain a 4-bit full adder we cascade four 1-bit full adders, by connecting the

Carry Out bit of bit column M to the Carry In of the bit column M+1, as shown

below. The Carry In of the Least Significant column is set to zero.

A3 B3 A2 B2 A1 B1 A0 B0

A B C in A B C in A B C in A B C in

C out S um C out S um C out S um C out S um

C out

S3 S2 S1 S0

• Example: Find the bit values of the outputs {Cout,S3..S0} of the full adder

shown below, if {A3..A0 = 1011} and {B3..B0 = 0111}.

Magnitude Comparator

The D Edge Triggered Flip Flop

The D edge triggered flip flop can be obtained by connecting the J with

the K inputs of a JK flip through an inverter as shown below. The D

edge trigger can also be obtained by connecting the S with the R inputs

of a SR edge triggered flip flop through an inverter.

D J Q Q D J Q Q

CLK CLK

K Q Q K Q Q

Logic Symbol CLK D QN+1 Function Logic Symbol CLK D QN+1 Function

D Q X Q D Q X Q

CLK 0 CLK 0

0 0

Q Q 1

1 1 1

The Toggle (T) Edge Triggered Flip Flop

The T edge triggered flip flop can be obtained by connecting the J with

the K inputs of a JK flip directly. When T is zero then both J and K are

zero and the Q output does not change. When T is one then both J and

K are one and the Q output will change to the opposite state, or toggle.

Flip Flops with asynchronous inputs (Preset and Clear)

Two extra inputs are often found on flip flops, that either clear or preset the

output. These inputs are effective at any time, thus are called asynchronous. If

the Clear is at logic 0 then the output is forced to 0, irrespective of the other

normal inputs. If the Preset is at logic 0 then the output is forced to 1,

irrespective of the other normal inputs. The preset and the clear inputs can not

be 0 simultaneously. In the Preset and Clear are both 1 then the flip flop

behaves according to its normal truth table.

PRESET

PR

0 0 X X

J Q

0 1 X X 1

1 0 X X 0

K Q 1 1 0 0 Q

CLR

1 1 0 1 0

CLEAR

1 1 1 0 1

1 1 1 1 Q’

JK Flip Flop With Preset and Clear:- Example

Complete the timing diagrams for :

(a) Positive Edge Triggered JK Flip Flop

(b) Negative Edge Triggered JK Flip Flop.

Assume that for both cases the Q output is initially at logic zero.

(a) (b)

CLK CLK

J J

K K

CLR CLR

PR PR

Q Q

Sequential circuit example 1

A0

2-to-1 SET

MUX

D Q

A1

CLR Q

Clock

1 2 3 4 5 6 7 8 9 10

Clock

A0

A1

D

Q

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