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Introduction to

CMOS VLSI
Design

Sequential Circuits
Outline
 Sequencing
 Sequencing Element Design
 Max and Min-Delay
 Clock Skew
 Time Borrowing
 Two-Phase Clocking

CMOS VLSI Design 2


Sequencing
 Combinational logic
– output depends on current inputs
 Sequential logic
– output depends on current and previous inputs
– Requires separating previous, current, future
– Called state or tokens
– Ex: FSM, pipeline
clk clk clk clk

in out
CL CL CL

Finite State Machine Pipeline

CMOS VLSI Design 3


Sequencing Cont.
 If tokens moved through pipeline at constant speed,
no sequencing elements would be necessary
 Ex: fiber-optic cable
– Light pulses (tokens) are sent down cable
– Next pulse sent before first reaches end of cable
– No need for hardware to separate pulses
– But dispersion sets min time between pulses
 This is called wave pipelining in circuits
 In most circuits, dispersion is high
– Delay fast tokens so they don’t catch slow ones.

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Sequencing Overhead
 Use flip-flops to delay fast tokens so they move
through exactly one stage each cycle.
 Inevitably adds some delay to the slow tokens
 Makes circuit slower than just the logic delay
– Called sequencing overhead
 Some people call this clocking overhead
– But it applies to asynchronous circuits too
– Inevitable side effect of maintaining sequence

CMOS VLSI Design 5


Sequencing Elements
 Latch: Level sensitive
– a.k.a. transparent latch, D latch
 Flip-flop: edge triggered
– A.k.a. master-slave flip-flop, D flip-flop, D register
 Timing Diagrams clk clk

Latch

Flop
– Transparent
D Q D Q

– Opaque clk

– Edge-trigger D

Q (latch)

Q (flop)

CMOS VLSI Design 6


Sequencing Elements
 Latch: Level sensitive
– a.k.a. transparent latch, D latch
 Flip-flop: edge triggered
– A.k.a. master-slave flip-flop, D flip-flop, D register
 Timing Diagrams clk clk

Latch

Flop
– Transparent
D Q D Q

– Opaque clk

– Edge-trigger D

Q (latch)

Q (flop)

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Latch Design
 Pass Transistor Latch
 Pros 
+
+ D Q
 Cons





CMOS VLSI Design 8


Latch Design
 Pass Transistor Latch
 Pros 
+ Tiny
+ Low clock load D Q
 Cons
– Vt drop Used in 1970’s
– nonrestoring
– backdriving
– output noise sensitivity
– dynamic
– diffusion input

CMOS VLSI Design 9


Latch Design
 Transmission gate

+
- D Q

CMOS VLSI Design 10


Latch Design
 Transmission gate

+ No Vt drop
- Requires inverted clock D Q

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Latch Design
 Inverting buffer 
+ D
X
Q
+

+ Fixes either 

• D Q


CMOS VLSI Design 12


Latch Design
 Inverting buffer 
+ Restoring D
X
Q
+ No backdriving

+ Fixes either 

• Output noise sensitivity D Q


• Or diffusion input

– Inverted output

CMOS VLSI Design 13


Latch Design
 Tristate feedback

+
X
– D Q

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Latch Design
 Tristate feedback

+ Static
X
– Backdriving risk D Q

 Static latches are now essential


CMOS VLSI Design 15


Latch Design
 Buffered input

+ X
D Q
+

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Latch Design
 Buffered input

+ Fixes diffusion input X
D Q
+ Noninverting

CMOS VLSI Design 17


Latch Design
 Buffered output  Q

+ D
X


CMOS VLSI Design 18


Latch Design
 Buffered output  Q

+ No backdriving D
X


 Widely used in standard cells 


+ Very robust (most important)
- Rather large
- Rather slow (1.5 – 2 FO4 delays)
- High clock loading

CMOS VLSI Design 19


Latch Design
 Datapath latch
 Q
+ X
D
-

CMOS VLSI Design 20


Latch Design
 Datapath latch
 Q
+ Smaller, faster X
D
- unbuffered input

CMOS VLSI Design 21


Flip-Flop Design
 Flip-flop is built as pair of back-to-back latches
 
X
D Q

 

  Q

X
D Q
 
 

 

CMOS VLSI Design 22


Enable
 Enable: ignore clock when en = 0
– Mux: increase latch D-Q delay
– Clock Gating: increase en setup time, skew
Symbol Multiplexer Design Clock Gating Design
 en

 

D 1
Latch

Latch

Latch
D Q Q D Q
0

en en

 en

 D 1
Flop

Q
0
Flop

Flop
D Q D Q
en
en

CMOS VLSI Design 23


Reset
 Force output low when reset asserted
 Synchronous vs. asynchronous
 
Symbol

Latch

Flop
D Q D Q

reset reset
Synchronous Reset

 Q   Q

reset reset
Q
D D
 

  

 

Q
Q 
Asynchronous Reset

 
reset
reset
D
D 
 

 
reset
reset


CMOS VLSI Design 24


Set / Reset
 Set forces output high when enabled

 Flip-flop with asynchronous set and reset




reset
set Q
D




set
reset

CMOS VLSI Design 25


Sequencing Methods
Tc

 Flip-flops

Flip-Flops
clk

 2-Phase Latches clk clk

 Pulsed Latches

Flop

Flop
Combinational Logic

2-Phase Transparent Latches


1
tnonoverlap tnonoverlap
Tc/2
2

1 2 1

Latch

Latch

Latch
Combinational Combinational
Logic Logic
Half-Cycle 1 Half-Cycle 1
Pulsed Latches

p tpw

p p
Latch

Latch
Combinational Logic

CMOS VLSI Design 26


Review Timing Definitions

CMOS VLSI Design 27


Timing Diagrams
Contamination and
Propagation Delays A tpd
Combinational
A Y
tpd Logic Prop. Delay Logic
Y tcd

tcd Logic Cont. Delay


clk clk tsetup
thold
tpcq Latch/Flop Clk-Q Prop Delay

Flop
D Q D
tccq Latch/Flop Clk-Q Cont. Delay tpcq
Q tccq
tpdq Latch D-Q Prop Delay

tpcq Latch D-Q Cont. Delay clk tsetup thold


clk
tccq tpcq

tsetup Latch/Flop Setup Time


Latch

D Q D tpdq
tcdq
thold Latch/Flop Hold Time Q

CMOS VLSI Design 28


Max-Delay: Flip-Flops
t pd  Tc    clk clk

Q1 D2

F1

F2
sequencing overhead Combinational Logic

Tc
1. rising edge of clk trigger F1
tsetup
clk
tpcq
2. data at Q1 after clk-to-Q
delay tpcq Q1 tpd

3. cont. logic delay to D2


D2
4. setup time for F2 before
rising edge of clk

CMOS VLSI Design 29


Max-Delay: Flip-Flops
t pd  Tc   tsetup  t pcq 
clk clk

Q1 D2

F1

F2
sequencing overhead Combinational Logic

Tc

tsetup
tpd is the time allow for clk
tpcq
combinational logic
Q1 tpd
design the CL block
satisfying the constraint D2

CMOS VLSI Design 30


Max Delay: 2-Phase Latches
1 2 1
t pd  t pd 1  t pd 2  Tc    D1 Q1 D2 Q2 D3 Q3
Combinational Combinational

L1

L2

L3
sequencing overhead Logic 1 Logic 2

1

2
Tc

D1 tpdq1

Q1 tpd1

D2 tpdq2

Q2 tpd2

D3

CMOS VLSI Design 31


Max Delay: 2-Phase Latches
1 2 1
t pd  t pd 1  t pd 2  Tc   2t 
pdq D1 Q1 Combinational D2 Q2 Combinational D3 Q3

L1

L2

L3
sequencing overhead Logic 1 Logic 2

1

assume that tpdq1 = tpdq2


2

propagation delay D1 Tc

to Q1, D2 to Q2 D1 tpdq1

Q1 tpd1

D2 tpdq2

Q2 tpd2

D3

CMOS VLSI Design 32


Max Delay: Pulsed Latches
t pd  Tc  max   p p

D1 Q1 D2 Q2

L1

L2
Combinational Logic
sequencing overhead
Tc

D1 tpdq

(a) tpw > tsetup


Q1 tpd
tpdq : D to Q propa. delay
D2
tcdq : D to Q contamination delay
p

tpcq : clk to Q propagation delay tpcq Tc tpw


Q1 tpd tsetup
(b) tpw < tsetup
D2

CMOS VLSI Design 33


Max Delay: Pulsed Latches
p p

t pd  Tc  max  t pdq , t pcq  tsetup  t pw  D1 Q1 D2 Q2

L1

L2
Combinational Logic

sequencing overhead
Tc

D1 tpdq

If the pulse is wide enough, tpw > (a) t pw


> tsetup
Q1 tpd
tsetup , max-delay constraint is similar
to the two-phase latches except only D2

one latch is in the critical path p

tpd < Tc - tpdq tpcq Tc tpw


Q1 tpd tsetup
(b) tpw < tsetup
D2
If pulse width is narrow than the
setup time, data must set up before
the pulse rises
tpd < Tc + tpw – tpcq – tsetup

CMOS VLSI Design 34


Min-Delay: Flip-Flops
tcd minimum logic contamination
clk
delay

tcd 
Q1

F1
CL

clk
If thold > tcd, the data can D2

F2
incorrectly propagate through F1
and F2 two successive flip flops
on one clock edge, resulting in clk
system failure
Q1 tccq tcd

D2 thold

CMOS VLSI Design 35


Min-Delay: Flip-Flops
tcd minimum logic contamination
clk
delay of CL block

tcd  thold  tccq


Q1

F1
CL

clk
1. rising edge of clk trigger F1 D2

F2
2. after clk-to-Q cont. delay
Q1 begins change clk

3. D2 begins to change after CL Q1 tccq tcd


cont delay
D2 thold
4. D2 should not change for at
least thold w.r.t. the rising clk, if
D2 changes it corrupts F2
so tcd  thold  tccq
CMOS VLSI Design 36
Min-Delay: 2-Phase
Latches 1

Q1

L1
CL

tcd 1,tcd 2 
2

D2

L2
1. Data pass through L1 from
rising edge of 1 tnonoverlap
1
2. Data should not reach L2 until
tccq
a hold time delay the previous 2

falling edge of 2 i.e. L2 becomes


Q1 tcd
safely opaque.

tcd 1,tcd 2  thold  tccq  tnonoverlap


D2 thold

We need tcd large enough to have correct


operation, meet thold requirement of L2

CMOS VLSI Design 37


Min-Delay: 2-Phase Latches
tcd 1,tcd 2  thold  tccq  tnonoverlap 1

Q1

L1
CL

Hold time reduced by


2
nonoverlap
D2

L2
Paradox: hold applies
twice each cycle, vs. 1
tnonoverlap

only once for flops. tccq


2

But a flop is made of two Q1 tcd


latches!
D2 thold

Contamination delay constraint applies to each phase of logic for latch-


based systems, but to the entire cycle of logic for flip-flops.

CMOS VLSI Design 38


Min-Delay: Pulsed Latches
p

tcd  Q1

L1
CL

p
Hold time increased
D2
by pulse width

L2
p
tpw
thold

Q1 tccq tcd

D2

CMOS VLSI Design 39


Min-Delay: Pulsed Latches
tcd  thold  tccq  t pw p

Q1

L1
CL

p
Hold time increased
D2
by pulse width

L2
p
tpw
thold

Q1 tccq tcd

D2

tccq + tcd  tpw + thold

CMOS VLSI Design 40


Time Borrowing
 In a flop-based system:
– Data launches on one rising edge
– Must setup before next rising edge
– If it arrives late, system fails
– If it arrives early, time is wasted
– Flops have hard edges
 In a latch-based system
– Data can pass through latch while transparent
– Long cycle of logic can borrow time into next
– As long as each loop completes in one cycle

CMOS VLSI Design 41


Time Borrowing Example
1

2
1 2 1
Latch

Latch

Latch
Combinational
(a) Combinational Logic
Logic

Borrowing time across Borrowing time across


half-cycle boundary pipeline stage boundary
1 2
Latch

Combinational Logic Latch Combinational


(b) Logic

Loops may borrow time internally but must complete within the cycle

CMOS VLSI Design 42


How Much Borrowing?
2-Phase Latches 1 2

 c   tsetup  tnonoverlap 
D1 Q1 D2 Q2
T

L1

L2
Combinational Logic 1
tborrow
2
1

2 tnonoverlap
Tc

tsetup
Tc/2 tborrow
Nominal Half-Cycle 1 Delay

D2

Pulsed Latches Data can depart the first latch on the rising edge
of the clock and does not have to set up until the
tborrow  t pw  tsetup falling edge of the clock on the receiving latch

CMOS VLSI Design 43


Clock Skew
 We have assumed zero clock skew
 Clocks really have uncertainty in arrival time
– Decreases maximum propagation delay
– Increases minimum contamination delay
– Decreases time borrowing

CMOS VLSI Design 44


Skew: Flip-Flops clk clk

Q1 D2

F1

F2
Combinational Logic
tpd : propagation delay of CL Tc

t pd  Tc   t pcq  tsetup  tskew 


clk
tpcq
tskew
tsetup
sequencing overhead
Q1
tpd tpdq

D2

tcd  thold  tccq  tskew clk

tcd : contamination delay of CL Q1

F1
CL

tccq + tcd  tskew + thold clk

D2

F2
Launching flop receives its
clock early, the receiving tskew

flop receives its clock late clk


thold

 clock skew effectively Q1 tccq

increases the hold time D2 tcd

CMOS VLSI Design 45


Skew: Latches
1 2 1
2-Phase Latches D1 Q1 D2 Q2 D3 Q3

 2t 
Combinational Combinational

L1

L2

L3
t pd  Tc  pdq
Logic 1 Logic 2

sequencing overhead 1

tcd 1 , tcd 2  thold  tccq  tnonoverlap  tskew 2

  tsetup  tnonoverlap  tskew 


Tc
tborrow 
2

Latch-based design, clock skew does not degrade performance


Data arrives at the latches while they are transparent even clocks are skewed.
Latch based design systems are skew-tolerant.

CMOS VLSI Design 46


Skew: Pulsed Latches
Pulsed Latches
t pd  Tc  max  t pdq , t pcq  tsetup  t pw  tskew 
sequencing overhead

tcd  thold  t pw  tccq  tskew

tborrow  t pw   tsetup  tskew 


If the pulse width is wide enough, the skew will not increase overhead
If the pulse width is narrow, skew can degrade the performance

CMOS VLSI Design 47


Two-Phase Clocking
 If setup times are violated, reduce clock speed
 If hold times are violated, chip fails at any speed
 An easy way to guarantee hold times is to use 2-
phase latches with big nonoverlap times
 Call these clocks 1, 2 (ph1, ph2)

CMOS VLSI Design 48


Safe Flip-Flop
In industry, use a better timing analyzer
– Add buffers to slow signals if hold time is at risk

  Q

X
D Q
 
 

 

Power PC 603 datapath used this flip-flop


CMOS VLSI Design 49
Differential Flip-flops
Accepts true and complementary
inputs
Produce true and complementary
outputs
Works well for low-swing inputs
such as register file bitlines and
low-swing busses

When  is low, precharge X, X’


When  is high, either X or X’ is
pulled down, cross-coupled
pMOS work as a keeper
Cross-coupled NAND gates work
as a SR latch capturing and
holding the data .

CMOS VLSI Design 50


Differential Flip-flops
Replace the cross-coupled NAND gates by a faster latch

CMOS VLSI Design 51


Summary
 Flip-Flops:
– Very easy to use, supported by all tools
 2-Phase Transparent Latches:
– Lots of skew tolerance and time borrowing
 Pulsed Latches:
– Fast, lowest sequencing overhead, susceptible to min-
delay problem

CMOS VLSI Design 52