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UNIT 2: COMPUTER ARITHMETIC

Addition and Subtraction

Two’s Compliment Representation
Signed Addition and Subtraction
Multiplication and division
Booths Algorithm
Division Operation
Floating Point Arithmetic Operation
Design of Arithmetic unit

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Half Adder / Full adder: Addition of two/three binary Digits.

Half-Adder: Combinational circuit that performs the arithmetic addition of two

bits.
Input variable: augends and addend bits.
The output: The sum and carry
The C output is 0 unless both input are 1.
The S output represent the least significant bit of
the sum.
Boolean Function:
S=X’Y + XY’ = X⊕Y
C =XY
Circuit Truth Table

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Half Adder / Full adder: Addition of two/three binary Digits.

Half-Adder: One that performs the addition of three bits (Two significant bits
and a previous carry).
Input variable: augends, addend bits and previous carry.
The output: The sum and carry
The C output is represent output carry.
The S output represent the least significant bit of
the sum.
Boolean Function:
S=X⊕Y⊕Z
C =XY + (X ⊕ Y)Z =XY+ (X’Y + XY’)Z
Circuit

Truth Table

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Arithmetic Addition: Arithmetic Addition and Subtraction of two number.

+ 6 00000110 - 6 11111010
+13 00001101 +13 00001101

+19 00010011 + 7 00000111

+ 6 00000110 - 6 11111010
- 13 11110011 - 13 11110011

- 7 11111001 - 19 11101101

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Arithmetic Micro-operation:

Symbolic Designation Description

R3 <- R1 + R2 Content of R1 plus R2 transferred to R3

R3 <- R1 - R2 Content of R1 minus R2 transferred to R3

R2 = R2 Complements the content of R2(1’sComplement)

R2 = R2 + 1 2’s Complement of content of R2

R3 = R1 + R2 + 1 R1 plus 2’s Complement of content of R2

R1 = R1 + 1 Increment the content of R1 by one

R1 = R1 - 1 Decrement the content of R1 by one

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Binary Adder: To implement add micro-operation we need;

Register to hold data
Digital component that perform arithmetic addition of two
bit and previous carry: i.e. Full Adder

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Binary Adder - Subtractor: The addition and subtraction operations can be

combined into one common circuit by including one exclusive OR gate with each
full adder. The Mode input M control the operation.
When M = 0 The circuit is an Adder
M = 1 The circuit is become a Subtractor

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Binary Incrementer: The Binary Incrementer micro-operation adds one to a

number in register.
If a 4 bit register has a binary value 0110, it will go to
01110 after it is incremented.
This micro-operation is easily implemented with a binary counter.

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4- bit Arithmetic Circuit:

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Addition and Subtraction of Signed Magnitude Number

Four basic Arithmetic Operation:

Addition, Subtraction, Multiplication and Divide
Arithmetic Processor: part of processor unit that execute arithmetic operation.
Arithmetic operation is specified in definition of instruction.
Data types resides in processor register.
Data is either decimal, Binary.
It may be either fixed point (Integer) or floating point (fraction).
Negative Number may be signed-magnitude or signed-complement
representation.

We Consider basic arithmetic operation for the following type of data:

Fixed point binary data in signed magnitude representation
Fixed point binary data in signed 2’s complement representation
Floating point binary data
Binary coded decimal data.

We designate the magnitude of two number A and B. When the signed number ared
added or subtracted, we find total eight different condition, depending on the sign
of the number and operation performed.

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Consideration for Basic Arithmetic Operation

Addition Algorithm:
When the sign of two magnitude are identical:
Add the two magnitude and attach the sign of A to the result.
When the sign of two magnitude are different:
Compare the magnitude and subtract the smaller number to larger.
Choose the sign of the result
To be same as A if A>B
Complement of the A if A<B
Magnitude are equal
Subtract B from A and make the sign of result positive.

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HARDWARE IMPLEMENTATION

Need: Two Register to hold magnitude of A (Accumulator), B and Result

Two Flip-flop to hold sign of As, Bs and Result
A parallel adder to perform micro-operation A+B
A comparator circuit to establish A>B, A=B and A<B
Two Parallel subtractor circuit to perform micro operation A-B & B-A
An Exclusive OR gate to determine sign of result with input As, Bs.
AVF (Add over-flow flip flop) hold the overflow bit.
When M = 0 the output of B is transferred to the adder, the input carry is 0 and the
output of the circuit is equal to A+B.
When M = 1 the 1’s Complement of B is applied to adder, the input carry is 1 and
output S = A+B+1, this is equal to A plus 2’s complement of B

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HARDWARE ALGORITHMS

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Addition and Subtraction of Signed 2’s Numbers Representation

<- Hardware Implementation

Algorithms: ->

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MULTIPLICATION

Multiplication: If the multiplier bit is 1, the multiplicand is copied down,

otherwise zeros are copied down. The number copied down in successive lines are
shifted one position left from the previous number. Finally the numbers are added.
If the sign is alike take positive sign otherwise take negative sign.
1. Instead of providing register to store and add
simultaneously as many binary number as there
are bits in multiplier, it is convent to provide an
adder for the summation of only two binary
number and successively accumulate the partial
product in a register.
2. Instead of shifting the multiplicand to the left, the
partial product is shifted to the right, which result
in leaving the partial product and the multiplicand
in the required relative position.
3. When the corresponding bit of the multiplier is
zero, there are no need to add all zeros to partial
product since it will not alter its value.

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MULTIPLICATION

Q & Qs: Multiplier and its sign

SC : Set to no. equals to no. of bit in multiplier (<)
B : Multiplicand
EA : E & A Hold partial product
EAQ : E, A and Q hold the over all result

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MULTIPLICATION
1 B SC 4 B SC

1 0 1 1 1 5 1 0 1 1 1 2

0 0 0 0 0 0 1 0 0 1 1 0 0 1 0 0 0 1 0 1 1 0

E A Q E A Q

2 B SC 5 B SC

1 0 1 1 1 4 1 0 1 1 1 1

0 0 1 0 1 1 1 1 0 0 1 0 0 0 1 0 0 0 1 0 1 1

E A Q E A Q

3 B SC 6 B SC

1 0 1 1 1 3 1 0 1 1 1 0

0 1 0 0 0 1 0 1 1 0 0 0 0 1 1 0 1 1 0 1 0 1

E A Q E A Q

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BOOTH MULTIPLICATION ALGORITHM

BMA: Provide a procedure for multiplying two binary integer in signed 2’s
complement representation
Principle: if 0 (in Multiplier) require: No addition operation & one Shift Operation
if 1 (in Multiplier) from bit weight 2k to 2m can be treated as 2k+1 - 2m
Ex: Number 001110 (+14) have string of 1’s from 23 to 21
So, k=3 & m=1, The Number can be represented as
2k+1-2m=24-21=16-2 = 14
So for Multiplication with number M can be written as
M*2k+1 - M*2m
Thus the product can be obtained by shifting the binary multiplicand M four time
to the left and subtract M shifted left once.

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BOOTH MULTIPLICATION ALGORITHM

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ARRAY MULTIPLIER

Concept: Checking the bit of multiplier one at a time and forming partial product
is a sequential operation that requires a sequence of add and shift micro-operation.
The multiplication of two binary number can be done with one micro-operation by
means of one combinational circuit that form the product bits all at once.
This is a fast way of multiplying two number since all it takes is the time
for signal to propagate through the gates that form the multiplication array.
However it requires a large number of gates, and for this reason it was not
economical until the development of integrated circuit.
For j Multiplier bits and k
multiplicand bit we need
j*k AND Gate and
Total (j-1) k-bit adders to
produced a product of j+k
bits.

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ARRAY MULTIPLIER (4*3 ) Multiplier

For j=3 Multiplier bits

and k=4 multiplicand bit
we need
3*4 AND Gate and
A total (j-1: 3-1=2) two
(k-bit) 4-bit adders to
produced a product of
(j+k) (3+4) 7 bits.

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DIVISION OPERATION

Division of two fixed-point binary number in signed-magnitude representation is

done with paper and pencil by a process of successive Compare, shift and subtract
operation.
It is simpler than decimal division because is the quotient digit are either 0 and 1
and there is no need to estimate how many times the dividend or partial remainder
fits into divisor.
• H/W Implementation: Instead of
shifting the divisor to the right, the
dividend, or partial remainder is
shifted to the left.
• Subtraction may be achived by
adding to the 2’s complement of
B.
• H/w need is identical to h/w
required for multiplication
• Sign are alike, the sign of
Quotient is plus
• Sign are unalike, the sign is
minus
•The sign of remainder is the same
as the sign of the dividend.
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DIVISION OPERATION

• If E=1, it signifies that A>=B

o A quotient bit 1 is inserted into Qn
oThe partial remainder is shifted to
the left to repeat the process
o Divisor is subtracted by adding its
2’s complements.
• If E=0, it signifies that A<B
o Quotient in Qn remains a 0
oThe value of A is added to restore the
partial remainder in A.
o Shift EAQ and add 2’s complement

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DIVISION OPERATION

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FLOATING POINT ARITHMETIC OPERATION

Basic Consideration: A Floating Point Number 0in computer register consist of

two parts: a mantissa m and an exponent e. The two parts represent a number
obtained from multiplying m times a radix r raised to the value of e: Thus
m*re
i.e. number 537.25 is represented as m=53725 and r=10 and e=3 and is interpreted
to represented the floating point number .53725*103
If a computer world length is 48 bit then fixed point integer will be represented as:
one bit must be reserved for sign
the range is (247-1) i.e. approximately ±1014
If a computer world length is 48 bit, Floating point number will be represented as:
36 bit for mantissa and 12 bit for exponent
Assuming fraction representation for mantissa, then the range of number
that can be represented
±(1-235)*22047
This number is derived from a fraction that contains 35 1’s, an exponent of
11 bits and the fact that 211-1=2047
So the largest possible number is 10615
(235-1)= approx 1010 means a 10 digit decimal number

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FLOATING POINT ARITHMETIC OPERATION

Basic Consideration: Arithmetic operation on floating point number is quick

complex, because for addition and subtraction of such number required alignment
of radix point and equal length of exponent part. Consider the sum of two number:
.5372400*102
+.1580000*10-1
Two possible solution either right or left shift for alignment of mantissa
Left Shift: causes a lost of MSB: cause a error
Right Shift: causes a lost of LSB: cause a loss in accuracy
So the number is rewrite as
.5372400*102 .56780*105
+ .0001580*102 -.56430*105
Result . 5373980*102 .00350*105
Overflow due to carry underflow due to zero in left

Re- Written as: 1) right shift with increase in exponent

2) left shift with decrement in exponent (.35000*103)

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FLOATING POINT ARITHMETIC OPERATION

Basic Consideration: Floating point multiplication and subtraction do not required

alignment of mantissa. The product can be formed by multiplying two mantissa and
adding the exponent. Division is accomplished by dividing the mantissa and
subtracting the exponent.
Multiplication and division of mantissa is quit common as the fixed point operation
but additional h/w specification for increment and decrement in exponent. The
exponent may be represented in any one of three representation: Signed magnitude,
signed 2’s Complement, signed 1’s complement.
Alternate representation may be possible called biased exponent;
Two digit exponent range 00 to 99
for positive exponent range from 99 to 50
the subtraction of 50 gives a positive value between 00 to 49
For Negative exponent range from 49 to 00
the subtraction of 50 gives a negative value between -1 to -50
So overall a magnitude comparator is required to calculate exponent.

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FLOATING POINT ARITHMETIC OPERATION

Basic Consideration: There are three register BR, AR and QR

Each Register is subdivided into two parts
The mantissa part has same uppercase letter symbol as in fixed point
representation i.e. in B, A and Q.
The exponent part uses the corresponding lower case letter symbol.
It is assumed that each floating point number has a mantissa in signed
magnitude representation and a biased exponent.
Sign of each number is hold in corresponding flip flop i.e. As, Bs and Qs.

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FLOATING POINT ARITHMETIC OPERATION

Addition and Subtraction: The

algorithm can be divided into four
consecutive part:
1. Check for Zeros
2. Align the mantissa
3. Add or subtract mantissa
4. Normalize the results.

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FLOATING POINT ARITHMETIC OPERATION

Multiplication: The Multiplication of two

numbers requires that multiplication of
mantissa and addition of exponent. No
comparison of exponent and alignment of
mantissa is necessary. Double –precision
product. The multiplication algorithm can be
subdivided into four part:
1. Check for Zeros
2. Add the exponent
3. Multiply the mantissa
4. Normalize the Product.

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FLOATING POINT ARITHMETIC OPERATION

Division: Floating point division requires

that exponent be subtracted and mantissas
divided. The division of mantissa is
fractional, so in fractional representation
the single precision dividend is placed in
Register A and register Q is cleared. If the
dividend is greater than or equal to divisor,
the dividend fraction is shifted to right and
its exponent is incremented by 1.The
algorithm can be subdivided into five part:
1. Check for Zeros
2. Initialize Register and Evaluate
3. Align the dividend
4. Subtract the exponent
5. Divide the mantissa.

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