Algorithmic state machine

charts for behavioral modeling

 ASM chart

• SM chart is also called an algorithmic state

machine (ASM) chart.
• It is easier to understand the operation of digital system
by inspection of the SM chart compared to a state graph.
• It describes behavior of digital circuits in much simpler
way
Components of an SM chart

A state box represents the

state of the system. The
state box contains a state
name followed by a slash
(/) and an optional output
list. After a state
assignment has been
made, a state code may be
placed outside the box at
the top.
This box will have two
branches. The condition
placed in the box is a
Boolean expression that
is evaluated to
determine which
branch to select.
It contains a conditional output
list. The conditional outputs
depend on both the state of the
system and the inputs.
 Construction of SM charts

• SM chart is constructed from SM blocks. Each SM block

contains exactly one state box, together with the decision
boxes and conditional output boxes associated with that
state.

• An SM block has one entrance path and one or more

exit paths.

• A path through an SM block from entrance to exit is

referred to as a “link path”.
Example of a SM block
Equivalent SM block
 Construction of SM charts

The construction of an SM chart for a sequential control

network is similar to that used to derive a state graph.
Steps are:
i) First draw a block diagram of the system that we are
controlling.
ii) Define the required input and output signals to the control
network.
iii) Then construct the chart that tests the input signals and
generates the proper sequence of output signals.
 Electronic Dice Game

• This is a game based on a dice, which will have 6 faces with numbers
1,2,3,4,5,6. In this game two dices will be thrown, and depending on
the sum of the numbers seen on the faces of the dices, the result is
decided.

• The rules of the game are as follows:

1. After the first ROLL of the DICE, the player wins if the SUM is 7 or
11.The player LOSES if the SUM is 2,3 or 12. Otherwise the SUM the
player obtained on the first ROLL is referred to as a POINT, and the
player must ROLL the DICE again.
• 2. On the second or subsequent ROLL of the DICE, the player WINS
if the SUM equals the point or loses if the SUM is 7. Otherwise, the
player must ROLL again until he or she finally WINS or LOSES or
RESETS (starts a new game).

• The inputs to the DICE game come from push buttons RB (Roll
Button) and RESET.

• RESET is used to initiate a new game. When the ROLL button is

pushed, the DICE counters count at high speed. So the values cannot
be read on the display. When the Roll Button is released the values in
the two counters are displayed and the game can proceed. If the WIN
light is not on, the player must push the Roll Button again.
Block diagram of the Electronic Dice Game
• Input signals to the control network are defined as follows:

• D7 = 1 If the sum of the dice (output of the counters) is 7

• D7, 11 = 1 If the sum of the dice is 7 or 11
• D2, 3,12 = 1 If the sum of the dice is 2,3 or 12
• Eq = 1 If the sum of the dice equals the number stored in the Point Register.
• RB = 1 When the reset button is pressed

• Outputs from the control network are defined as follows:

• ROLL = 1 Enables the dice counters

• Sp = 1 Causes the sum to be stored in the Point Register
• Win = 1 turns on the win light
• Lose = 1 turns on the Lose light
Flow chart for DICE game
SM chart for DICE game
State Graph for Dice Game
Control Unit: Behavioral VHDL
Code
Serial adder
module serial_adder ( A,B, rst, clock, sum);
input [7:0] A,B;
input rst,clock;
output [7:0] sum;
reg [3:0] count;
reg s,NS,PS;
wire [7:0] qa,qb;
wire run;
parameter S0=0,S1=1;
shiftrne shift_A (clk,1’b0,rst,run,A,qa);
shiftrne shift_B (clk,1’b0,rst,run,B,qb);
shiftrne shift_sum (clk,s,rst,run,8'b0,sum);
//adder fsm
//output and next state combinational circuit
always @(qa or qb or ps)
case (PS)
S0: begin
s = qa[0]^qb[0];
if (qa[0] & qb[0]) NS=S1 ;
else NS=S0;
end
S1: begin
s = qa[0] ~^qb[0];
if (~qa[0] & ~qb[0])
NS=S0; else NS=S1;
end
default : NS=S0;
endcase
always @(posedge clock)
if (reset) PS<=S0;
else PS<=NS;
//control the shifting process
always @(posedge clock)
if (reset) count = 4’b1000;
else if (run) count = count - 1;
assign run=|count;
endmodule
// shift register
module shiftrne ( clk,s,rst,en,din,q);
input [7:0] din;
input s,rst,en,clock;
output [7:0] q;
reg [7:0] q;
always @(posedge clock)
if (rst) q <= din
else if (en)
q<={s,q[7:1]};
endmodule
 ASMD chart: Algorithmic state
machines and datapath
• An ASMD contains the annotation describing the datapath
operations and identify the signals produced by the controller
to cause the operation.
• ASMD establish a clear relationship between controller and
datapath
• Register operation that operates concurrently with state
transitions are represented on path of the chart
 Behavioral models of counters
and shift registers

Counters
Simple counter with synchronous and
asynchronous reset