RoBA Multiplier With Brent-Kung Adder For Higher Speed And

Better Energy Efficient Applications

B.Jyothi Presented By A.Kavya
H.Afrin S.Jagadiesh

Under the Guidance of

K.K.Gouse, M.Tech,MIE
Assistant Professor

DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

GATES INSTITUTE OF TECHNOLOGY, GOOTY.
 Abstract

 We proposed an approximate multiplier that is high speed yet energy

efficient.
 This approach is based on rounding of the operands to the nearest exponent
of two.
 RoBA Multiplier with Kogge-Stone adder is suggested by Reza Zendegani
for high speed and energy efficient Applications.
 The proposed approach suggested by us is to replace kogge-stone adder in a
RoBA Multiplier with Brent-Kung adder for increased speed and better
energy efficient.
 The proposed approach is applicable to both signed and unsigned
multiplications.
 Introduction

 Energy minimization is one of the main design requirements in almost any

electronic systems.
 Digital signal processing (DSP) blocks are key components of these
portable devices for realizing various multimedia applications.
 The computational core of these blocks is the arithmetic logic unit where
multiplications have the greatest share among all arithmetic operations
performed in these DSP systems.
 Therefore, improving the speed and power/energy-efficiency characteristics
of multipliers plays a key role in improving the efficiency of processors.
 RoBA Multiplier

• The idea behind the RoBA multiplier is to make use of the easy of

operation by rounding the operands to the nearest exponent of two (2 n).

• First, denote the rounded numbers of the inputs of A and B by A r and Br
respectively.
• Multiplication of A and B based on
A × B ∼= Ar × B + Br × A − Ar × Br .
• Ar × Br , Ar×B, and Br×A may be implemented by using shifters.
Block Diagram of RoBA Multiplier
 Prior Art Method-1

 The Vedic multiplier is based on an algorithm urdhava triyakbhyam

(vertical and cross wise) of ancient indian vedic mathematics.
 It is applicable to all cases of multiplication.
 In this process adder will be run based on the Ripple carry adder. If the
number of bits increases the carry generation and propagation will
increases, Due to this delay increases.
 The main drawback of this system, for complex multiplications, the system
becomes more complex due to this the energy consumed by the system
increases and delay increases.
 Prior Art Method-2
 Multiplication of A and B of RoBA Multiplier is based on
 A × B ∼= Ar × B + Br × A − Ar × Br .
 Ar × Br , Ar×B, and Br×A may be implemented shifter.
 In this process adder will be run based on the Kogge-Stone algorithm.
 Kogge-Stone Adder is a parallel prefix form carry look ahead adder .

Kogge-Stone Adder
 Proposed Method
• In this proposed Method, the adder block is replaced by Brent-Kung adder.It is
also a parallel pefix adder.
• Because in Kogge-stone Adder the number of gray cells and black cells are
more when compared to Brent-Kung Adder.
• By using this Brent-Kung Adder the delay is still decreases and size of the
circuit also reduces.
•The parallel prefix addition is done in 3 steps.
1.Pre-processing stage
2. Carry generation network
3. Post processing stage

Brent-Kung Adder
Pre-processing stage:
 In this stage we compute, the generate and propagate signals are used to generate
carry input of each adder. A and B are inputs. These signals are given by the
equation 1&2.
 Pi=A^iBi
 GI=Ai.Bi
Carry generation network:
 In this stage we compute carries corresponding to each bit. Execution is done in
parallel form [4].After the computation of carries in parallel they are divided into
smaller pieces. carry operator contain two AND gates , one OR gate. It uses
propagate and generate as intermediate signals.
 P(i:k) =P(i:j). P(j-1:k)
 G(i:k) =G(i:j)+(G(j-1:k). P(i:j))
Post processing stage:
 This is the final stage to compute the summation of input bits. it is same for all
adders and sum bit equation given

 Si= Pi Ci
 Ci+1=(Pi.C0) + Gi
 Schematic Diagrams
Koggestone Adder Brent Kung Adder
 Advantages and Applications of Proposed method

Advantages:
• Speed of the system increases.
• Decreases in Energy Consumption.

Applications:
• Portable devices such as mobile phones, tablets.
• Different electronic gadgets.
 DESIGN TOOLS AND LANGUAGE

• Xilinx 14.7 Version.

• Verilog code can be used for design implementation.
 Conclusion
 Hence the proposed Multiplier, has an high accuracy, which was based on
rounding of the inputs in the form of 2n.
 In this way, by using this approximate multiplier improving speed and
energy efficiency at a price of small error.