MICRO-OPERATIONS

M. Husnain Raza
Muhammad Kashif
Saqib Raza
Introduction of MICRO-OPERATION

 Computer executes the program

 Program consists on sequence of instruction cycle
 Each instruction cycle is made up of Smaller units or
smaller cycles like fetch , indirect , interrupt and execute
 Each smaller cycle consists on series of steps
 These steps are known as micro-operation.
Execution of program consists on
sequential execution of instruction.
Each instruction executed during
instruction cycle that made up of
subcycles. The execution of subcycle
consist on one or more small
operations called micro-operation.
Micro-Operation
Instruction cycle

 Computer execute program in instruction cycle.

 Each instruction cycle consists on fetch , indirect ,
interrupt and execute cycle
 Every instruction cycle must contain fetch and execute
cycle.
Registers used in Instruction cycle

 Memory Address Register: Connected on address buses

of system bus and specify the address in memory for
read and write operation.
 Memory Buffer Register: Connected on Data buses of
system bus and contains last value read from memory or
data to store in memory
 Program Counter: Contains address of next instruction
 Instruction Register: Holds last fetched instruction.
Fetch cycle

 It occurs in each instruction cycle.

 It used to fetch instruction from memory.

 At the beginning of fetch cycle , address of next instruction is in PC.

1. Moves the Address of PC in MAR(Memory address register)
2. Desired address placed on the address bus, control unit issue the READ
signal on control bus.
3. Result appears in data bus and copied into MBR
4. Also increment in PC
5. Move the contents of MBR into IR
Fetch cycle
Fetch Cycle

 Fetch cycle consists on 3 steps and 4 micro-operation.

T1: MAR  PC
T2: MBR  Memory
PC  PC+I
T3: IR  MBR

I is instruction length
T is time unit
 First time unit: Move the content of PC to MAR

 Second time unit: Move the contents of memory location in MBR ,

Increment I in PC

 Third Time unit: Move the contents of MBR in IR

 One micro-operation addition is used to avoid the duplication. It performs

by ALU .
Indirect Cycle

 When instruction is fetched next step is fetch source operands.

 There are two method direct addressing allowed and indirect addressing
allowed
 Indirect cycle must be execute before execute cycle.

 Micro-operation of INDIRECT CYCLE

T1: MAR  IR(Address)
T2: MBR  Memory
T3: IR(adrdress)  MBR(address)
 The address field of the instruction is transferred to the
MAR. this is then used to fetch the address of the
operand. Finally Address field of IR is updated from MBR.
So now it contains a direct rather than an indirect
address.
The Interrupt Cycle

 At the completion of the execute cycle a test is made to check any

enabled interrupt have occurred.
 Nature of interrupt cycle may be different for different machines.

 Micro-operation of Interrupt cycle

1. T1: MBR  PC
2. T2: MAR  save-address
PC  Routine-Address ( start of interrupt processing routine)
3. T3: Memory  MBR
The Execute Cycle

 Fetch , indirect and interrupt are simple and predictable

 Each have small and fixed sequence of micro-operations and repeated
each time.
 But it is not true about execute cycle.
 Because of variety of opcodes, there are number of different sequence of
micro-operations.
 ADD R1, X
Add the contents of the location X to register R1.

1. T1: MAR  IR(address)

2. T2: MBR  memory
3. T3: R1  (R1) + (MBR)

Begin with IR containing ADD instruction.

The content of location X is incremented by
1. if the result is 0 next instruction skip

1. T1: MAR  IR(address)

2. T2: MBR  memory
3. T3: MBR  MBR + 1
4. T4: memory  MBR
if (MBR=0) then (PC(PC +I))
Instruction Cycle

 Each phase of instruction cycle can be decomposed into a sequence of

micro-operations.
 A new 2-bit register called instruction cycle code(ICC) is used to designates
the state of the processer in terms of which portion of cycle it is in:
00: fetch
01: Indirect
10:Execute
11: Interrupt
 The indirect cycle is always followed by the execute cycle and The interrupt
cycle is always followed by the fetch cycle