DESIGN OF

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POWER AND
AREA
EFFICIENT
APPROXIMATE
MULTIPLIERS
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ABSTRACT
 Approximate computing can decrease the design complexity
with an increase in performance and power efficiency for
error resilient applications.
 The proposed approximation is utilized in two variants of 16-
bit multipliers. Synthesis results reveal that two proposed
multipliers achieve power savings of 72% and 38%,
respectively, compared to an exact multiplier.
 They have better precision when compared to existing
approximate multipliers. Mean relative error figures are as
low as 7.6% and 0.02% for the proposed approximate
multipliers, which are better than the previous works.
 Performance of the proposed multipliers is evaluated with an
image processing application, where one of the proposed
models achieves the highest peak signal to noise ratio.
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EXISTING SYSTEM
 In applications like multimedia signal processing and
data mining which can tolerate error, exact computing
units are not always necessary. They can be replaced
with their approximate counterparts.
 Research on approximate computing for error tolerant
applications is on the rise. Adders and multipliers form
the key components in these applications.
 In , approximate full adders are proposed at transistor
level and they are utilized in digital signal processing
applications.
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 Their proposed full adders are used in accumulation of partial

products in multipliers. To reduce hardware complexity of
multipliers, truncation is widely employed in fixed-width
multiplier designs.
 Then a constant or variable correction term is added to
compensate for the quantization error introduced by the
truncated part .
 Approximation techniques in multipliers focus on
accumulation of partial products, which is crucial in terms of
power consumption. Broken array multiplier is implemented in,
where the least significant bits of inputs are truncated, while
forming partial products to reduce hardware complexity
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DISADVANTAGES:
 More Logic complexity
 More power and more delay
Block diagram
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OVER VIEW OF MULTIPLIER

 Multiplication is a fundamental operation in most
signal processing algorithms. Multipliers have
large area, long latency and consume considerable
power.
 Multiplication involves mainly 3 steps
 1. Partial product generation
 2. Partial product reduction
 3. Final addition
 A 3/31/2019

X P
B
Multiplication Algorithm
X= Xn-1 Xn-2 ………..……X0 Multiplicand
Y=Yn-1 Yn-2……………….Y0 Multiplier

Yn-1X0 Yn-2X0 Yn-3X0 …… Y1X0 Y0X0

Yn-1X1 Yn-2X1 Yn-3X1 …… Y1X1 Y0X1
Yn-1X2 Yn-2X2 Yn-3X2 …… Y1X2 Y0X2
… … … …
…. …. …. …. ….

Yn-1Xn-2 Yn-2X0 n-2 Yn-3X n-2 …… Y1Xn-2 Y0Xn-2

Yn-1Xn-1 Yn-2X0n-1 Yn-3Xn-1 …… Y1Xn-1 Y0Xn-1
------------------------------------------------------------------------------------------------------------------------
-----------------
P2n-1 P2n-2 P2n-3 P2 P1 P0
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1. Multiplication Algorithms
Implementation of multiplication of binary numbers boils down to how to do the
additions. Consider the two 8 bit numbers A and B to generate the 16 bit product P. First
generate the 64 partial Products and then add them up.
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A

B
X P

Array Multiplier

 Regular structure based on add and shift

algorithm.

 Addition is mainly done by carry save algorithm.

 Sign bit extension results in a higher capacitive

load and
slows down the speed of the circuit.
A

B
XAddition with CLA
P

a3 a2 a1 a0
b0
A = a3a2a1a0

B = b3b2b1b0

a3 a2 a1 a0
b1

Ci
Cout Four-bit Adder 0
n
a3 a2 a1 a0
b2

Cout Four-bit Adder Cin 0

a3 a2 a1 a0
b3

Cout Four-bit Adder Cin 0

Product (A*B)
A

B
X P

Array Multiplier with CSA

A3 A2 A1 A0
P03 P12 0 P02 P11 0 P01 P10 0 P00
**Pij =Ai Bj

F.A F.A F.A

Total of 16 Aj Bi B0
gates
B1 Ci Si Ci Si Ci Si

B2
0i3 P13 P22 P21 P20
0 j3 B3

F.A F.A F.A

Pij Ci Si Ci Si Ci Si

P23 P32 P31 P30

F.A F.A F.A

Ci Si Ci Si Ci Si

P33 0

F.A F.A F.A

Ci Si Ci Si Ci Si

R7 R6 R5 R4 R2 R1 R0
R3
 A

X P

Critical Path with Array Multipliers

B

FA FA FA HA

FA FA FA HA

FA FA FA HA

Two of the possible paths for the Ripple-Carry based 4*4 Multiplier
Area = (N*N) AND Gate + (N-1)N Full-Adder

Delay = τ HA + (2N-1) τ FA
INTRODUCTION TO DADDA
MULTIPLIER
 The Dadda multiplier was designed by the scientist
Luigi Dadda in 1965. Its looks similar to Wallace
multiplier but slightly faster and required less
gates.
 Dadda Multiplier was defined in three steps
 Multiply the each bit of one argument with the
each and every bit of other argument and continue
until all arguments are multiplied
 Reduce the number of partial products to two
layers of full and half adders.
 Group the wires in two numbers, and add them
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PROPOSED SYSTEM
 The proposed multiplier in saves few adder circuits in partial product
accumulation. In , two designs of approximate 4-2 compressors are presented and
used in partial product reduction tree of four variants of 8 × 8 Dadda multiplier.

 The major drawback of the proposed compressors in is that they give nonzero
output for zero valued inputs, which largely affects the mean relative error (MRE)
as discussed later. The approximate design proposed in this brief overcomes the
existing drawback. This leads to better precision.
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 In static segment multiplier (SSM) proposed in [6], m-bit

segments are derived from n-bit operands based on leading 1
bit of the operands.
 Then, m × m multiplication is performed instead of n × n
multiplication, where m<n. Partial product perforation (PPP)
multiplier in omits k successive partial products starting from
jth position, where j ∈ [0, n-1] and k ∈ [1, min(n-j, n-1)] of a
n-bit multiplier. In [8], 2 × 2 approximate multiplier based on
modifying an entry in the Karnaugh map is proposed and used
as a building block to construct 4 × 4 and 8 × 8 multipliers.
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 In inaccurate counter design has been proposed for use in

power efficient Wallace tree multiplier.
 A new approximate adder is presented in which is utilized for
partial product accumulation of the multiplier. For 16-bit
approximate multiplier in [10], 26% of reduction in power is
accomplished compared to exact multiplier.
 Approximation of 8-bit Wallace tree multiplier due to voltage
over-scaling (VOS) is discussed in Lowering supply voltage
creates paths failing to meet delay constraints leading to error.
ADVANTAGES OF PROPOSED
METHOD
 Re-silent errors are reduced
 Power consumption decreased
 Circuit area reduced
RESULTS
TOOLS USED
 XILINX 14.5
THANK YOU
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ADVANTAGES:

 Less Logic complexity

 Less power and more delay