The Structure of THE

Multiprogramming
System
Dijkstra 1968
Aiman Erbad
Outline

 Contributions
 Platform & Systems goals
 System Components
 Layered structure
 Questions
Contributions

 Layered Structure of OS

 Concurrent Programming (semaphores)

 Memory segments (virtual addresses)

 Proof of correctness of the system

Definitions

 Core memory  Main Memory

 Drum  Secondary storage – Disk

 Sequential Processes not sequential

execution
Platform (Hardware)

 Dutch Electrologica EL X8 computer

 32K core memory (cycle time 2.5usec)
 512K words drum (1024 words per track, 40msec rev )
 Low capacity channels supporting peripherals
 (3 paper tape readers and punches, printer, plotter, and 2 teleprinter)

 An indirect addressing (suited for stack

implementation)
 A sound control of interrupts and peripherals
System Goals
(1) Reduce the turn-around time for programs of short duration
(2) Efficient use of peripheral devices
(3) Efficient use of memory and central processor
(4) Support programs that need the flexibility of general purpose
computer without the capacity and the processing power
This system is not intended for multi-access system.
They don’t share common data, they only share configuration
and procedure library.
Major Mistakes

 Attempt a perfect installation

 Late debugging
 Prevention better than cure
System Components

 Storage allocation

 Processor allocation

 System Structure
 Storage Allocation

 Distinction between memory units “pages”

and information units “segment”

 Segment have “virtual address” that are

mapped to the page “physical address”

Virtual Address Magic Physical Address

Processor Allocation
 Society of sequential processes
 Process per program
 Process per peripheral
 2 Processes for segment controller and message interpreter

 These processes cooperate via explicit mutual synchronization

(semaphores)
 Mutual exclusion semaphores
 Private semaphore
System Structure

 THE has five Layers

 Each layer builds an abstraction hiding the

details below it

 Each layer uses only the functionality of the

lower layers
System Structure
 Five Layers
 Layer 0: CPU Scheduler (Process Allocator)
 Handles CPU scheduling and handling clock interrupts (Virtual CPU)
 Layer 1: Memory Manager (Segment Controller)
 Handles automatic storage allocation (Virtual memory)
 Layer 2: Console Manager (Message Interpreter)
 Handles user input and processes output (Virtual console)
 Layer 3: Device Managers
 Handle devices and provide buffering (input and output)
 Layer 4: User Programs

The original slide was from www.cs.washington.edu/451

Layered Structure

Hardware
Layered Structure

CPU Scheduling

Hardware
Layered Structure

Memory Management

CPU Scheduling

Hardware
Layered Structure

Console Manager

Memory Management

CPU Scheduler

Hardware
Layered Structure

Device Manager

Console Manager

Memory Management

CPU Scheduler

Hardware
Layered Structure

User Programs

Device Manager

Console Manager

Memory Management

CPU Scheduler

Hardware
Layered OS Structure
 Pros
 Modularity and information hiding
 Each layer can be tested and verified independently

 Cons
 Difficult to define and order layers
 Not flexible (real systems are more complex)
 Poor performance
 Disjunction between model and reality
Monolithic Structure

user programs

OS everything

hardware
Monolithic OS
Command Interpreter

Information Services

Error Handling Accounting System

File System

Protection System

Memory Secondary Storage

Process Management Management Management

I/O System
 Microkernel structure
user firefox powerpoint
processes apache

user mode
file system network
system paging
processes threads scheduling

communication

kernel
microkernel low-level VM processor
protection control

hardware
System Goals
(1) Reduce the turn-around time for programs of short duration

(2) Efficient use of peripheral devices

(3) Efficient use of memory and central processor

(4) Support programs that need the flexibility of general purpose

computer without the capacity and the processing power
Conclusion

 Contributions
 Platform & Systems goals
 System Components
 Layered structure
 Questions
Mutual Exclusion
 begin semaphore mutex; mutex := 1;
parbegin
begin L1:
P(mutex);
critcal section 1;
V(mutex);
remainder of cycle 1;
go to L1 end;
begin L2:
P(mutex);
critical section 2;
V(mutex); remainder of cycle 2;
go to L2 end
parend end
Private Semaphore

Process 1
P(mutex)
If resource available then
V(private semaphore)
V(mutex)
P(private semaphore)
Private Semaphore

Process 2
P(mutex)
"modification and inspection of state variables”
V(private semaphore)
V(mutex)
Proving the Harmonious
Cooperation
 Notion of cyclic processes having “homing
position” and “unstable situation”
 Proof outline:
 Process performing a task can generate only a finite
number of tasks
 System cannot be at rest if there are still pending
tasks
 All processes will eventually be in homing position
(no deadlock)
References
 "The structure of the “THE”-multiprogramming system",
by E. Dijkstra, Communications of the ACM, Vol. 11, No.
5, 1968, 341--346
 OS lecture slides – University of Washington
www.cs.washington.edu/451
 Dijkstra Home page – University of Texas
http://www.cs.utexas.edu/users/EWD/
 Class Presentation by S. Stipic and M. Dimitrov
www.cs.ucf.edu/courses/cop5611/spring05/item/THE.pdf