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Based on
Expected Hit Count
ISCA 2017
25 June 2017 Cache Replacement Policy Based on Expected Hit Count CRC-2 2
Intro
Problem
• Off-chip accesses stall the processor for hundreds of
cycles
• Limited cache size
o Latency
o Limited silicon area
One Solution
• Improving replacement policy
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Replacement Policy
Observation
80
60
40
20
1 2 3 4 5 6 7+
Number of Remaining Hits
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Predicted Remaining 0 5 2 1 1
Hit Count
Comparator
EHC
• Hit-count predictor
• Hit-counter per block
• number of hits of the block since the entrance to the cache
• Store the number of recently hit counts in a table (HHT)
o Set-associative structure
o LRU replacement policy
o Indexed by block’s tag
o To save area
HHT Structure
Updating Metadata
HHT Index
HHT Tag
HHT
A B C D E
Default HitCnt
RRPV HitCnt RRPV HitCnt RRPV HitCnt RRPV HitCnt
RRPV (0)
Tag EHC(E)
Predicted Remaining HC = |E – HitCnt|
A 4 Value= Predicted Remaining HC – RRPV
HHT
... ...
D 2
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Example
RRPV
A B C D E
5 2 5 2 0 1 0 2 6 0
4 2 5 3 2 2 5 5 0 1 0 1 2 2 0 0 7 0 6 1
Tag A C D E
Minimum HHT
Value EHC 4 0 2 7
Evict B
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Why baseline?
Methodology
● Benchmarks
o SPEC CPU2006
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• DRRIP
• Assigns re-reference interval prediction value (RRPV) for
each block
• Evicts block with maximum RRPV
• SHiP
• Classifies blocks into two categories
• Good Blocks and Bad Blocks
• Enhances DRRIP by predicting dead-on-arrival blocks
• EVA
• Reconciles hit probability and expected lifetime by measuring
time in cache as forgone hits
• Evicts candidate with lowest EVA
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Trace Results
10%
0%
bzip cactusADM mcf xalanc Average
-10%
-20%
-30%
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Cycle-Accurate Simulation
DRRIP SHiP EVA EHC
Performance normailzed to LRU
1.2
No clue to
determine the Binary
1.15 dead blocks classification
1.1
1.05
0.95
cactusADM mcf xalanc Average Mix1 MIX2 Average
Single-Core Multi-Core
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Hardware overhead
Hardware optimization
1.1
1.05
1
0.95
0.9
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Conclusions
EHC:
• Low-cost-yet-effective replacement policy
• Evicts block that predicted to have the
minimum expected remaining hit count
• Cache-like structure for HHT
• 31.75KB area overhead for a 2MB cache
• 19.75KB area overhead over baseline (DRRIP)
• 3.4% Performance improvement over baseline
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Thank you
for
your attention!