UNIT – III

Control Unit Design

• A control unit or CU is circuitry that directs operations within a
computer'sprocessor. It lets the computer's logic unit, memory, as well
as both input and output devices know how to respond to instructions
received from a program. Examples of devices that utilize control
units include CPUs and GPUs.

• A control unit works by receiving input information that it converts

into control signals, which are then sent to the central processor. The
computer's processor then tells the attachedhardware what operations
to carry out. The functions that a control unit performs are dependent
on the type of CPU, due to the variance of architecture between
different manufacturers.
 Timing and Control
• A master clock generator controls the timing for all
registers in the basic computer.

• The clock pulses are applied to all F/F’s and registers in

system.

• These clock pulses does not change the state of a register

unless the register is enabled by a control signal

• The control signals are generated in the control unit and

provide control i/p’s for the MUX’s in the common bus,
processor registers, and micro-operations for the
accumulator.
Hardwired control organization

• The control logic is implemented with gates,

F/Fs, decoders, and other digital circuits

• It has advantage that it can be optimized to

produce a fast mode operation

• It requires changes in wiring (if the design has

to be modified)
Micro-programmed control organization
• The control information is stored in a control
memory (ROM).

• Bit slow operation compare to Hardwired.

• The control memory is programmed to initiate the

required sequence of micro-operations.

• Any required change can be done by updating the

micro-program in control memory.
 Block diagram of Control Unit ( Hardwired control)

Control Unit = Control Logic

Gates + 3 X 8 Decoder + 4 X 16
Decoder + Instruction Register +
4-bit Sequence Counter

An instr. read from memory is

placed in IR.

Op-code of bits 12-14 are

decoded using 3x8 decoder.

Bit 15 of instr. is transferred to

F/F – I.

Bits 0-11 are applied to control

logic gates
Counter is cleared to ‘0’ to make the next active
timing signal as ‘T0’.

SC can be INC / CLR synchronously, and it is

INC to provide sequence of timing signals.

The output of counter is decoded into 16 timing

signals T0 – T15.
CASE STUDY
 1’S Complement Multiplier
• Hardwired Control Unit
– Classical Method
– One Hot Method.
Design of 1’s Complement Multiplier
Control Signals of Multiplier
Flowchart of 1’s Complemet Multiplier
 Micro Programmed Control Organization
Topics

• M.P.C Organization

• Address Sequencing

• Micro-instruction Format

• Micro-program Sequencer
Control Unit

• Initiate sequences of micro-operations. ( H/W & MPC )

• Control signal (that specify micro-operations) in a bus-

organized system is a binary variable.

• Control binary variable – Control Word (Programmed)

• A control Unit – Micro-programmed control unit.

• Each Control Word in a Control Memory consists of a
Microinstruction

• The microinstruction specifies one or more Micro operations.

• A sequence of microinstruction constitutes a Micro-program.

• Static microprogramming : Control Memory = ROM

– Control words in ROM are made permanent during the hardware production.

• Dynamic microprogramming : Control Memory = RAM

– RAM can be used for writing (a writable control memory)
• A memory which is a part of control unit is Control Memory.

• A computer which employs a M.P.C org will have 2 memories

– Main memory ( user program – m/c instructions/data)
– Control memory ( fixed micro-program )

Micro-program consists of micro-instructions

Which specify diff control signals for execution of
Micro-operations.

These micro-inst’s generates the micro op’s to FETCH the

inst’s, to evaluate the EA, to EXECUTE the operation & to
return the control to REPEAT the cycle for next instruction.
 Block diagram of M.P.C unit

• Control memory (ROM) – permanently stored.

• CAR specifies the address of micro-inst’r.
• CDR holds a micro –inst’r. read from memory (Pipeline Reg)
• CW specify one or more micro-op’s for data processing
• Once all these op’s are executed then control should determine
the next address, which is computed in N.A.G ckt. & then
transfers into CAR to read next inst’r. ( Program sequencer)
 Address Sequencing

• Address Sequencing = Sequencer : Next Address Generator

• Selection of address for control memory
• Micro-inst’s are stored in Control Memory in groups, where
each group specifying a ROUTINE.
Address Sequencing Capabilities : control memory address

1) Incrementing of the control address register

2) Unconditional branch or conditional branch, depending on

status bit conditions

3) Mapping process ( bits of the instruction address for control

memory )

4) A facility for subroutine return

Selection of address for control memory
 Micro-Instruction format
• The 20 bits of micro-instruction are divided
into four fractional parts.
• F1 (3)
• F2 (3)
• F3 (3)
• CD (2)
• BR (2)
• AD (7)
 Micro-instruction code format (20)

Micro-operations are sub-divided into three fields of 3-bits each.

The 3-bits in each field are encoded to specify seven distinct micro-operations.

This gives a total of 21 micro-operations.

No more than three micro-operations can be chosen for a micro-instruction, one from
each field.
Symbols and binary code for micro-instruction fields
•
 Microprogram Sequencer
• Micro-program Sequencer select the next address for control memory.
MUX 1
Select an address source and route to CAR
CAR + 1
JMP/CALL
Mapping
Subroutine Return
MUX 2
» Test a status bit and the result of the
test is applied to an input logic circuit
» One of 4 Status bit is selected by
Condition bit (CD)
Design of Input Logic Circuit
» Select one of the source address
(S0, S1) for CAR
» Enable the load input(L) in SBR
Input Logic Truth Table