The Register File and ALU

CS/COE 0447 (term 2181)

Jarrett Billingsley
 Class announcements
● Today/Tuesday's lectures will be helpful for the project
o Who's not gonna be here Tuesday? :^)
● Since there was no lab last week…
o This week's lab will be the size of/count for two labs.
o It's due Thursday 11/30 by 11:59PM (two weeks)
o Charge your laptops and do it in the car/bus/plane lol
● EC assignment will definitely be out before break as well
● Only 3 lectures of new material after break, then review
● Final will be cumulative!

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How the display unit works now
Display Unit
3 C
8 5
4 2
2 D
put r1, 0 4
8 8
4
3
5 3
5
Next High This way we can show
put r2, 1 Byte 2
C a 16-bit number in an
2
D instant instead of the
display changing
Displayed while we write to it.
Value (1 or 2
registers)

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 A few more tips…
● Do NOT use the registers' 0 input.
● If you clear the display unit's registers using the 0 input, a D Q

put followed by a clr would never show the value.

00
WE
o This is because the 0 input is asynchronous: it doesn't 0
care about the clock.
o The description says: If Write Enable = 1 AND Clear = 1,
on the rising edge of the Clock all registers should be
set to 0.
● The upper 7 bits of the immediate input are ignored.
o We're just using the lowest bit to change the behavior.
● To change the display components' background color, set
the alpha to 255 as well. (0 means transparent.)

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 The Register Files

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 The MIPS register file
● In the instruction add t0, t1, t2, how many registers are read?
o How many are written?
o How many different registers are accessed?
There's one input or There are two output
write port.
Register or read ports.

It needs a clock signal.

File Each port can read a
What other control WE rd rs rt different register.
signals does it need?

How about a And inputs to select

write enable? the registers?
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It doesn't have to be this way
CISC CPUs usually have small RISC CPUs usually have 32* mostly-
sets of registers, and many have interchangeable registers: MIPS,
special purposes or behaviors. RISC, SPARC, ARMv8, AVR, RISC-V…
8086 z80 6502 PDP8 r0 r1 r2 r3 r4 r5 r6 r7
ax a f A AC r8 r9 r10 r11 r12 r13 r14 r15 32/64
bx b c X
r16 r17 r18 r19 r20 r21 r22 r23 bits
cx d e Y 12 bits
r24 r25 r26 r27 r28 r29 r30 r31
dx h l
si ix 8 bits
Why is this? Well, what do you
di iy remember about the differences
sp sp between RISC and CISC?
bp
16 bits
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 Tug-of-war
● Register file design is constrained by several design requirements.
Compilers love lots of
ISA says instructions identical registers! …but there are diminishing returns.
have 2 operands
and 1 destination.
Fast L1 cache? Not as
…except for this one many regs needed.
instruction that has D
D QQ Q
2 destinations. D
Multi-issue CPU: need to
read 4 regs and write 2.
Humans like intuitive
assembly language!
More registers means
With lots of registers, more silicon…
function calls are faster! …but context switches
are slower.
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 A word of advice
● You will see many imperfect designs in your life.
● But in engineering, perfection isn't always the goal.
o Everyone has to work within the constraints they're given.
● And if everyone does something the same way…
o There are probably problems/constraints you don't know about.
o Don't waste your time reinventing the wheel.
o Find out why it's done that way first.
● When it comes to register files, 32 registers is just a nice number.
Not too many, not too few, a nice middle-ground.
● Also don't be a judgmental ass about someone else's design because one, it's shitty, and two, they know
more about why it was designed that way, so you're just being presumptuous

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 Reading from one register
● You have two registers, and you want to choose one to read.
What kind of component chooses?
D Q

A WE
83

29
83
D Q Reading from a register is
technically combinational.
B 29
WE
0
1 A read port is made of a
select signal, a MUX, and a
data output.

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 Writing
● For the write port, we only want to write to one register at a time.
● We'll have a select signal again…

When should we write to A? D

Q
Do we ALWAYS write to a select = 0
register? How about in WE
83 A
beq A, 3, top? WE = 1

When should we write to B? D Q

select = 1
WE
29
B
WE = 1

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 Close the door
● When a register's write enable is 0, what happens to the data?
● We can hook up the data input to all registers at once.

Data D Q

WE
83 A
Only the register with
WE=1 will store the data.
D Q

WE
29
B

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 Chekhov's Gun
● There's a component we haven't seen in a while which only sends
an input value to one of its outputs.
D Q
WE
0
WE
83 A
WE

D Q
1
0 WE
0 29
B
WE
A write port is made of a select signal, a data
input, a write enable, and some kinda logic to
send the write enable to one register.

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The ALU
 Arithmetic and Logic Unit
● An ALU does all the stuff we talked about in the previous unit.
● Remember lab 4?

This is a very simple ALU: it takes two 4-bit values, and either
adds or subtracts them, based on a control signal.

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 It really is that straightforward
● An ALU can be entirely made of combinational logic.
A

+
B
-
The Op(eration)
Op signal controls what
the ALU does.

Again: do everything, but only pick the thing you need.

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 Save Our Silicon
● An ALU can be a pretty sizeable chunk of space.
● You might reuse the ALU hardware for multiple purposes.
and t0, t2, t5 t2
bne t0, 0, lab1 t0 t2 & t5
b lab2 PC
t0 - 0
t5 PC + 24
0
24

But we can't do all three at the same time. (Structural Hazard!)

So either duplicate parts of the ALU, or use multi-cycle.

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 Bit slicing
● The book makes the ALU
like this.
● This approach is called
bit slicing: build a 1-bit
ALU, then copy-and-paste it.
● Then they make it more
confusing???
● It might be what they
really use when designing
a chip, but it's not great for learning.
● It does the same thing but is way harder to understand.

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 What about multiply and divide though??
● MIPS also does them separately because they're slow.
mult t0, t1
add t2, t3, t4 Main
Then we run other stuff…
and t2, t2, a2 ALU
...
It sends the multiplication
move v0, t2 off to a separate unit.
mflo v1
D Q
…and later, ask for +-
the result.
D Q
ctrl

×÷ Unit
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 Hey, that's neat actually
● By making the multiply/divide unit separate from the rest of the
CPU, we can do fun things like overclock it.
● Maybe the CPU runs at 2 GHz, but the divider at 8 GHz.
o Now the divider does 4 steps on each main CPU cycle.
● Combine this with a fast predictive divider that computes 4 bits of
quotient every cycle…
o And now you have a divider that can do a 32÷32-bit division in
only 2 CPU cycles in the best case!
● But…
o What should happen if the program tries to get the quotient
before the division is done?
o How do we "pause" the CPU when that happens?
● These issues are (mostly) solved by superscalar execution.

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 Ah, whatever, use as much silicon as you want
● A multi-issue CPU can run multiple instructions in parallel.

add t0, t0, a0 And 2 ALUs, of course.

sub t1, t1, a1
These are two independent t0
calculations. Let's do them ALU
at the same time! a0 1
Register
Now we need four read
ports and two write ports.
File t1
ALU
a1 2

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