Sense Amplifier Classification

 Voltage Mode SA
 Improved Wilson SA
 Current Mode SA
 Cascade SA
 Dynamic load latch type Current mode SA
 Hybrid type Current mode SA
 Charge Transfer SA
 Fully Symmetrical SA
 Active Current SA
 Active Regulated SA
 Slope SA
 Memristor based SA
 PMOS Bias Type (PBT) SA
 Voltage Mode SA [2010]

Block A- Selected Reading Path Block B- Current Mirror

Transistor M3-M6 and Inverters INV2-INV4 constitute the output stage
FG-Floating Gate
SG- Selecting Gate
 Improved Wilson SA [2005]

1. Uses Wilson Mirror Cell

2. Provides increased output impedance compared with conventional
 Current Mode SA [1996]

Uses 3V supply and 9ns sensing time, Suited for future memory devices. SA Circuit
consists of cross coupled structure (T1 and T2), switches (T3, T4), two diode
connected transistors (DL, DR) and an equalising device (TE)
Cascode Current Mode SA [2005]

Conventional sense amplifier uses simple current mirror cell. In order to

minimize the effect of output impedance a cascode configuration can be used
Dynamic Load Latch Type CSA[2001]

MN1 and MN2 are fed by

inputs to reduce input
impedance. Advantage is
wide dynamic range and
low operating voltage
Hybrid Type Current Mode SA[2001]

Waveforms
Charge Transfer SA [2003]

Operation of CTSA is based on

charge re-distribution from high
bit-line capacitance to the low
capacitance of the nodes Sa and
Sa# .

Circuit consists of two parts.

First one common gate cascode
formed by M1, M3 and M5.
Second is cross coupled
inverters
 Fully Symmetrical SA[2004]

Ensures zero systematic offset, adequate rejection of disturbs coming from capacitive
coupling with noisy substrate, power supply, and ground.
Symmetric because all PMOS and NMOS transistors have same aspect ratios
 Active Current SA [2005]

To minimize the loading effects, the input impedance can be decreased

with an active gain element in the feedback loop of conventional
current mirror cell
 Active Regulated SA [2005]

To boost the output impedance without stacking more transistors , a

regulated current mirror cell can be used
 Slope SA [2015]

The slope SA generates the digital signal sense out (SO) & the corresponding
timing information is proportional to the bit-line voltage slope and not to the
absolute BL voltage level
Memristor based SA [2013]
PMOS Bias Type(PBT) SA [2005]

PMOS Transistors are used for the bitline loads

 Enhanced PBT SA [2005]

Gain element is used to increase the bit-line loads and to reduce the effect
of bias voltage on delay