SDR

Software-Defined Radio (SDR)

• Radio transceivers perform the baseband processing entirely in software:
modulation/demodulation, error correction coding, and compression.

• Software-Defined Radio (SDR) refers to the technology wherein software

modules running on a generic hardware platform consisting of DSPs and
general purpose microprocessors are used to implement radio functions such
as generation of transmitted signal (modulation) at transmitter and
tuning/detection of received radio signal (demodulation) at receiver.

• Military programs such as SPEAKeasy sought to enable communication and

interoperability between several military standards
 Benefits of SDR
• Flexible
• Reduced Obsolescence
• Enhances Experimentation
• Brings Analog and Digital World Together
 Benefits of SDR (Cont..)
• Reprogrammable
• Multiband/Multimode
• Networkable
• Simultaneous voice, data, and video
• Full convergence of digital networks and radio
science.
 Advantages of SDR
• Ease of design
– Reduces design-cycle time, quicker iterations
• Ease of manufacture
– Digital hardware reduces costs associated with manufacturing
and testing radios
• Multimode operation
– SR can change modes by loading appropriate software into
memory
• Use of advanced signal processing techniques
– Allows implementation of new receiver structures and signal
processing techniques
• Fewer discrete components
– Digital processors can implement functions such as
synchronization, demodulation, error correction, decryption,
etc.
• Flexibility to incorporate additional functionality
– Can be modified in the field to correct problems and to upgrade
Digital Radio
 Digital Radio
• The antenna section, which receives (or transmits) information
encoded in radio waves.

• The RF front-end section, which is responsible for

transmitting/receiving radio frequency signals from the
antenna and converting them to an intermediate frequency
(IF).

• The ADC/DAC section, which performs analog-to-

digital/digital-to-analog conversion.
• The digital up-conversion (DUC) and digital down-conversion
(DDC) blocks, which essentially perform modulations of the
signal on the transmitting path and demodulation of the signal
on the receiving path.

• The baseband section, which performs operations such as

connection setup, equalization, frequency hopping,
Coding/decoding, and correlation, while also implementing the
link layer protocol
 Block Diagram
Software Defined Radio

Antenna
RF IF Baseband

Bandpass ADC/DAC
Filter DSP

Variable Local
Frequency Oscillator
Oscillator (fixed)
 Block Diagram
Software Defined Radio
Antenna
RF IF Baseband

ADC/DAC DSP

Local
Oscillator
(fixed)
 Block Diagram
Software Radio
Antenna
RF IF Baseband

ADC/DAC DSP
 Levels of SDR
Tier Name Description
Implemented using hardware components.
Tier 0 Hardware Radio (HR)
Cannot be modified
Software Controlled Only control functions are implemented in
Tier 1
Radio (SCR) software: inter-connects, power levels, etc.
Software control of a variety of modulation
Software Defined
Tier 2 techniques, wide-band or narrow-band
Radio (SDR)
operation, security functions, etc.

Ideal Software Radio Programmability extends to the entire system

Tier 3
(ISR) with analog conversion only at the antenna.
Ultimate Software
Tier 4 Defined for comparison purposes only
Radio (USR)

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 Evolution of Software Defined
Radio
•In the mid-1990s military radio systems were invented in which software
controlled most of the signal processing digitally, enabling one set of hardware to
work on many different frequencies and communication protocols.

•The first (known) example of this type of radio was the U.S. military’s
SPEAKeasy I and SPEAKeasy II radios, which allowed units from different
branches of armed forces to communicate for the first time.

•However, the technology was costly and the first design took up racks that had to
be carried around in a large vehicle.

•SPEAKeasy II was a much more compact radio and was the first SDR with
sufficient DSP resources to handle many different kinds of waveforms.

•Companies such as Vanu, AirSpan, and Etherstack currently offer SDR products
for cellular base stations.
 Evolution of Software Defined Radio

 Vanu Inc., a U.S.-based company, has been focusing on the commercial

development of SDR business since 1998.

It received a lot of attention in 2005 with its Anywave TM GSM base station,
which became the first SDR product to receive approval under the newly
established software radio regulation.

The Anywave base station runs on a general-purpose processing platform and

provides a software implementation of the BTS (base transceiver station), BSC
(base station controller), and TRAU (transcoder and rate adaptation unit) modules
of the BSS(base sation subsystem).

It supports GSM and can be upgraded to GPRS and Edge.

 The product was first deployed in rural Texas by Mid Tex Cellular in a trial,
where Vanu base station showed successfully how it could concurrently run a time
division multiple access (TDMA) and a GSM network, as well as remotely upgrade
and fix bugs on the base station via an Internet link.
 Evolution of Software Defined Radio

In March 2005 Airspan released the first commercially available SDR based
IEEE 802.16 base station.

The AS.MAX base station uses pico arrays TM and a reference software
implementation of the IEEE 802.16d standard.

The picoarray is a reconfigurable platform that is 10 times faster in processing

power than today’s DSPs.

The AS.MAX base station promises to be upgradeable to the next generation

mobile 802.16e standard and so has the potential to offer a future-proof route to
operators looking to rolling out WiMAX services.

Significant progress in the SDR development in the open-source research and

university communities: Example GNU radio
Hardware Architecture of Software
Defined Radio
Software Architecture of Software
Defined Radio
 Architectures of SDR
1. SDR Architecture Based on Current-Generation Technology

Notes to Figure 1:
• DUC: Digital upconverter DDC: Digital downconverter
• CFR: Crest factor reduction DPD: Digital predistortion
• PA: Power amplifier LNA: Low noise amplifier
2. Software Architecture of SDR
1. The system uses a generic hardware platform with
programmable modules (DSPs, FPGAs,
microprocessors) and analog RF modules. The
operating environment performs hardware resource
management activities like allocation of hardware
resources to different applications, memory
management, interrupt servicing and providing a
consistent interface to hardware modules for use by
applications.

2. In SDR system, the software modules that implement

link-layer protocols and modulation/demodulation
operations are called radio applications and these
applications provide link-layer services to higher layer
communication protocols such as WAP and TCP/IP.
 Typical Components of SDR
• Analog Radio Frequency (RF) receiver/transmitter in the 200 MHz to
multi-gigahertz range.
• High-speed A/D and D/A converters to digitize a wide portion of the
spectrum at 25 to 210 Msamples/sec.
• High-speed front-end signal processing including Digital Down
Conversion (DDC) consisting of one or more chains of mix + filter +
decimate or up conversion.
• Protocol-specific processing such as Wideband Code Division
Multiple Access (W-CDMA) or OFDM, including spreading/de-
spreading, frequency-hop-and chip-rate recovery, code/decode
functions, including modulation/demodulation, carrier and symbol
rate recovery, and channel interleaving/de-interleaving.
• Data communications interface with carrier networks and backbone
for data I/O and command-and-control processing, usually handled
by general purpose ARM or PowerPC processors and Real-Time
Operating System (RTOS).
Software Radio Layering Model
bytes bytes
Data Link Link Data
Link Framing Framing Link
bits bits
Channel Channel
Encoding Decoding
bits bits
Line Line
Encoding Decoding
symbol symbol
Modulation Demodulation

discrete signal discrete signal

Multiple Multiple software
Access Access
discrete signal discrete signal
D/A A/D hardware
Converter Converter
continuous signal continuous signal
RF RF
Physical Physical
Transmitter Receiver
continuous signal wireless medium continuous signal
25
 Dual Mode (2G/3G) Transceiver
Configuration
DSP
FRONT WB DE
A/D RAKE DEM
END FIL SPREAD

for 3G System
WB
P.A. SPREAD MOD CODEC
FIL
ANT
CONT
FRONT NB
DEM
END FIL
for 2G System

NB
P.A. MOD CODEC
FIL

CONT

26
 W-CDMA,CDMA2000
Algorithm
Partitioning
Modulator
CDMA2000
Demodulator
S/W part(DSP)
Despreader
Searcher WCDMA
Time Tracker S/W part(DSP)
Conversion AFC
RF to IF Channel estimator H/W part
Lock detector (ASIC)
and A/D
RAKE combiner
Power control
Flexible H/W part
Channel codec
(FRBA or FPGA)
Rate matching
Multiplexing

Baseband processing

I/O controller Process controller Program memory

27
16
Essential Functions of the Software Radio
 Essential Functions of the Software Radio

• Multiband technology, first of all, accesses more than one RF band of

c o m mu n i c a t i o n s ch an n e l s a t o n c e . .

• Channel Set includes RF channels, but radio nodes like Personal

Communications System (PCS) base stations and portable military radios
also interconnect to fiber and cable; therefore these are also included in the
channel set. .

• The channel encoder expands to RF/ Channel Access, IF Processing and

Modem. Antennas and RF conversion that span multiple RF bands
comprise the RF/ Channel Access function. .

• IF Processing may include filtering, further frequency translation,

space/time diversity processing, beam forming and related functions.
 Essential Functions of the Software Radio

• Multimode radios generate multiple air interface waveforms (“modes”)

defined principally in the modem, the RF channel modulator-demodulator.
These waveforms may be in different bands and may span multiple bands.

• The source and channel coders become the multiple personalities. A

personality combines RF band, channel set (e.g. control and traffic
channels), air interface waveform, and related functions.

• Although many applications do not require Information Security (INFOSEC),

there are incentives for its use. Authentication reduces fraud. Stream encipherment
ensures privacy. Both help assure data integrity.

• Transmission security (TRANSEC) hides the fact of a communications event (e.g.

by spread spectrum techniques ). INFOSEC is therefore included in Figure ,
although the function may be null for many applications.
• In addition, the source coder / decoder pair must now be expanded to include
the data, facsimile, video and multimedia sources implicit in Figure
.

• Some sources will be physically remote from the radio node, connected via
the Synchronous Digital Hierarchy (SDH), a Local Area Network (LAN),
etc., through Service & Network Support .
• .
• These functions may be implemented in multithreaded multiprocessor
software orchestrated by a Joint Control function .

• Joint control assures system stability, error recovery, timely data flow, and
isochronous streaming of voice and video. As radios become more advanced,
Joint Control becomes more complex, evolving toward autonomous selection
of band, mode, and data format .

• Any of the functions may be singleton (e.g. single band versus multiple
bands) or null, further complicating joint control .
• Beamforming supports additional users and enhances quality of service (QoS).
Beamforming today requires dedicated processors, but in the future, these algorithms
may time-share a Digital Signal Processor (DSP) pool along with the Rake receiver
and other modem functions .
•
• Joint source and channel coding also yields computationally intensive waveforms.
Dynamic selection of band, mode, and diversity as a function of QoS introduces
large variations into demand, potentially causing conflicts for processing resources
.

• Channel strapping, adaptive waveform selection and other forms of data rate agility
further complicate the statistical structure of the computational demand. In addition,
processing resources are lost through equipment failures .
• .
• Joint control integrates fault modes, personalities and support functions on a limited
resource of Applications-Specific Integrated Circuits (ASICs), Field Programmable
Gate Arrays (FPGAs), DSPs and general-purpose computers to yield a reliable
telecommunications object .
 A Mathematical Model of Plug-And-Play
Architecture
• This model may be used:
• 1. To identify top level plug-and-play interfaces;
• 2. To predict and control system performance;
• 3. To define a reference model that facilitates standards setting; and
• 4. To derive architecture principles for product evolution strategies.

Topological Structure Of An Illustrative Radio

 Architecture Goals

• A successful plug-and-play modular architecture entails at least the following:

1. Compatibility: The structure of plug-and-play modules must be
compatible with that of the software radio environment - arcs must have nodes to
plug into.
2. Controllability: Such modules must be controllable under module
composition.
3. Predictability: Module composition must preserve radio service-defining
properties of the system and when control is exerted, it must not have unintended
consequences.
Quantifying Degrees of Programmability

Hardware Topology Indicates Incompatibility of Download

• FPGAs are in principle completely programmable. In practice, they are more
programmable than ASICs, but subject to gate and interconnect constraints.

• Programmable radios have been based almost entirely on reconfigurable FPGAs .

Intuitively, however, the field programmability of an FPGA is more constrained
than that of a DSP chip, because of the possibility of running out of usable gates on
the FPGA .

• Suppose an advanced timing recovery algorithm, comprising, say,10% of the FPGA

area is to be downloaded to the radio. As shown, it is incompatible with the gate use
of the existing timing recovery logic .

• It may be possible to redefine the entire personality of the FPGA to accommodate

the new logic. In this case, the download bandwidth increases from the 10% needed
for the increment to 100% of the personality, a 900% increase in the size of the
download .

• It is also possible that a moderately populated (70%) FPGA will be unable to

accommodate the 10% download because of hardware constraints such as the
required placement of I/O buffers, lack of state registers where needed, etc.
• A similar topological model of a DSP chip with multiple Direct Memory Access
(DMA) channels is shown in Figure .

• The additional 10% of DSP code associated with the advanced timing recovery
logic (now implemented in software) is accommodated provided the Random
Access Memory (RAM) or electronically programmable Read Only Memory
(ROM) has available space .

• In this case, the memory map allocates logic to RAM/ ROM hardware. DSPs may
appear easier to program than FPGAs because RAM allocation can be
accomplished by a compiler while allocation of logic to gates and interconnect in an
FPGA generally requires an experienced designer .

• New waveforms also seem to outgrow the gates on an FPGA more easily than they
outgrow the program memory of a DSP subsystem .

• On the other hand, the topology of timing constraints of DSP software may be more
constraining than the timing of an equivalent FPGA .

• This is in part because logic in an FPGA can run at the system clock rate, while the
speed of DSP code may be one to three orders of magnitude less than the system
clock .
• .
• Complex or Reduced Instruction Set Computers (CISC/RISC) provide less
hardware acceleration than DSP chips.

• To quantify the degree of flexibility of DSP, CISC and RISC processors, one again
defines an appropriate topological space. Let {ISA} be the space of single-
instruction register-state transformations of a processor with a given Instruction Set
Architecture (ISA).

• From an arbitrary initial state, a DSP has many more edges connecting reachable
data states than a CISC processor that in turn has more arcs than a RISC processor.
So, from the perspective of {ISA} topology, the RISC processor is the simplest and
thus in some sense the most general programmable hardware platform, CISC is
more complex and DSP the most complex of the fixed ISA machines.

• Performance of high quality code underscores these differences. DSP code that
employs zero-overhead loops with full register stacks and processing elements
yields higher throughput than CISC code of a processor with the same system
clock, memory and I/O delays.

• FPGAs, on the other hand, effectively have a variable ISA that makes them even
more computationally efficient than DSPs, CISC and RISC machines, with an
attendant loss of generality.
Software Radio Phase Space
 Top Level Component Topology
Attributes of Top Level Software Radio Functional Components
Minimum Interfaces Define Topological
Properties
Top Level Interface Topologies