Module-3

Peak detector
• Holding capacitor(C1) is charged via the low output resistance of op-
amp A1.
• If amplification is required, it can be done by making R2>R1
• During +ve half cycle: D1 is FB and D2 is RB. Vi getting across Vc and it
is charged up to Vp. V0=VC1=VP
• Vi<Vp the voltage across capacitor remains at Vp because it does not
find any path for discharge.V0=Vp
• During –ve half cycle: A1 acting as inverting amplifier. V0=Vp
Design Consideration
• C1 should be kept as small as possible, so that it can be rapidly
charged to allow its voltage to easily follow changes in the peak input.
• C1 should hold its charge for a given time.
• Id Should be kept minimum by using A2 as BIFET.
Voltage follower peak detector
• This circuit presents a very high input impedance.
• Both op-amps acts as voltage follower . So Vo=Vc
• Capacitor discharge current are Ib to A2 and reverse leakage current
of D2.
• When Vi>Vc, output of A1 is +ve, D2 FB & A1 acts as voltage follower,
charging C1 to Vp
• When Vi<Vp, Vc=Vp, inverting terminal of A1 remains at Vp. Therefore
output of A1 is –ve , reversing D2 &D1 FB.
• A2 is BIFET opamp , A1 can be op-amp
• D2 should have a very low reverse leakage current.
Sample and hold circuit
It samples instantaneous amplitude of a signal voltage at any point in its waveform and holds the
voltage level constant until the next sample is acquired
• Modifications:
• FET: Alternatively connect and disconnect capacitor at the output of
op-amp A1.
• D1 and D2 inverse parallel connection to avoid op-amp(A1) going into
saturation.
• Q1 is switched on A1 and A2 acts as a single voltage follower. Vc=Vi
• Waveform:
• Q1 is repeatedly switched on and off by providing pulse waveform to
gate terminal of Q1.
• Vi is sufficiently –ve to drive FET gate voltage below its pinch off
voltage .
• Vi must to positive, approximately Vc to ensure complete turn on of
FET.
• If Vi>Vc while Q1 is off, C1 charges rapidly to Vi when Q1 is ON
• If Vc>Vi, C1 is discharged to a level of Vi when Q1 is ON.
• When Q1 is off . C1 holds the sampled voltage until next sampling
instant, giving step type capacitor voltage.