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B.Tech. EN-5TH SEMESTER
8086 MICROPROCESSOR
Intel 8086
Intel 8086 was launched in
1978.
It was the first 16-bit
microprocessor.
This microprocessor had
major improvement over
the execution speed of
8085.
It is available as 40-pin Dual-
Inline-Package (DIP).
Intel 8086
• It is available in three
versions:
– 8086 (5 MHz)
– 8086-2 (8 MHz)
– 8086-1 (10 MHz)
• It consists of 29,000
transistors.
Intel 8086
It has a 16 line data bus.
And 20 line address bus.
It could address up to 1
MB of memory.
It has more than 20,000
instructions.
It supports multiplication
and division.
Block Diagram of Intel 8086
General Segment
Purpose Registers
Registers, &
Pointers & Instruction
Index Pointer
Registers
Address Lines
Data Lines
BHE/S7, RD,
WR,
INTA, ALE,
DT/R,
DEN
CLK
VCC Control
GND Lines
MN / MX
Block Diagram of Intel 8086
• Intel 8086 contains two independent
functional units:
Segment Registers
Instruction Pointer
6-Byte Instruction Queue
Execution Unit
Execution Unit contains:
General Purposes Registers
Stack Pointer
Base Pointer
Index Registers
ALU
Flag Register
Instruction Decoder
Timing & Control Unit
Functions of Bus Interface Unit
It handles transfer of data and addresses between the
processor and memory / IO.
It reads data from memory and I/O devices.
It writes data to memory and I/O devices.
It computes and sends out addresses.
It fetches instruction codes.
It stores fetched instruction codes in a FIFO register
called QUEUE.
Instruction Queue
To increase the execution speed, BIU fetches as
many as six instruction bytes ahead to time from
memory.
All six bytes are then held in first-in-first-out 6-
byte register called instruction queue.
Then all bytes are given to EU one by one.
This pre-fetching operation of BIU may be in
parallel with execution operation of EU, which
improves the execution speed of the instruction.
Functions of Execution Unit
It receives opcode of an instruction from the QUEUE.
It decodes it and then executes it.
It tells BIU where to fetch the instructions or data from.
It contains the control circuitry to perform various
internal operations.
It has 16-bit ALU, which can perform arithmetic and
logical operations on 8-bit as well as 16-bit data.
Pipelining
While EU executes instructions, BIU fetches
instructions from memory and stores them in
the QUEUE.
BIU and EU operate in parallel independent of
each other.
This type of overlapped operation of the
functional units of a MP is called Pipelining.
Registers of Intel 8086
• Intel 8086 contains following registers:
General Purpose Registers
Pointer and Index Registers
Segment Registers
Instruction Pointer
Status Flags
General Purpose Registers
• There are four 16-bit general purpose
registers:
AX
BX
CX
DX
General Purpose Registers
• Each of these 16-bit registers are further
subdivided into two 8-bit registers.
AX AH AL
BX BH BL
CX CH CL
DX DH DL
General Purpose Registers
AX Register: AX register is also known as accumulator
register that stores operands for arithmetic operation
like divided, rotate.
BX Register: This register is mainly used as a base
register. It holds the starting base location of a memory
region within a data segment.
CX Register: It is defined as a counter. It is primarily
used in loop instruction to store loop counter.
DX Register: DX register is used to contain I/O port
address for I/O instruction.
Pointer and Index Registers
• Following four registers are under this
category:
Stack Pointer (SP)
Base Pointer (BP)
Source Index (SI)
Destination Index (DI)
Pointer and Index Registers
Stack Pointer (SP):
The function of SP is same as the function of SP in
Intel 8085.
It stores the address of top element in the stack.
Condition Flags
Control Flags
Status Flags
• Following are the nine flags:
Carry Flag (CF): This flag is set if there is a carry / borrow after an
integer arithmetic.
Parity Flag (PF): This flag is used to indicate the parity of result. If
the result contains even number of 1’s, the Parity Flag is set and for
odd number of 1’s, the Parity Flag is reset.
Condition Flags
Zero Flag (ZF): It is set; if the result of arithmetic
or logical operation is zero else it is reset.
Sign Flag (SF): In sign magnitude format the sign
of number is indicated by MSB bit. If the result of
operation is negative, sign flag is set.
Overflow Flag (OF): It occurs when signed
numbers are added or subtracted. An OF indicates
that the result has exceeded the capacity of
machine.
Control Flags
Control flags are set or reset deliberately to
control the operations of the execution unit.
Control flags are as follows:
Trap Flag (TP):
It is used for single step control.
It allows user to execute one instruction of a program
at a time for debugging.
When trap flag is set, program can be run in single step
mode.
Control Flags
Interrupt Flag (IF):
It is an interrupt enable / disable flag.
If it is set, the INTR interrupt of 8086 is enabled
and if it is reset then INTR is disabled.
It can be set by executing instruction STI and can
be cleared by executing CLI instruction.
Control Flags
Directional Flag (DF):
It is used in string operation.
If it is set, string bytes are accessed from higher
memory address to lower memory address.
When it is reset, the string bytes are accessed from
lower memory address to higher memory address.
It is set with STD instruction and cleared with CLD
instruction.
Pin Diagram of Intel 8086
AD0 – AD15
Pin 16-2, 39 (Bi-directional)
• These lines are multiplexed bi-
directional address/data bus.
• During T1, they carry lower order
16-bit address.
• In the remaining clock cycles, they
carry 16-bit data.
• AD0-AD7 carry lower order byte of
data.
• AD8-AD15 carry higher order byte
of data.
A19/S6, A18/S5, A17/S4, A16/S3
Pin 35-38 (Unidirectional)
• This is an acknowledgement
signal from slower I/O devices
or memory.
• It is an active high signal.
• When high, it indicates that the
device is ready to transfer data.
• When low, then
microprocessor is in wait state.
RESET
Pin 21 (Input)
• It is a system reset.
• It is an active high signal.
• When high, microprocessor
enters into reset state and
terminates the current activity.
• It must be active for at least
four clock cycles to reset the
microprocessor.
INTR
Pin 18 (Input)
• It is an interrupt request
signal.
• It is active high.
• It is level triggered.
NMI
Pin 17 (Input)
• It is a non-maskable interrupt
signal.
• It is an active high.
• It is an edge triggered
interrupt.
TEST
Pin 23 (Input)
51
Minimum Mode
INTA
Pin 24 (Output)
• This is an interrupt
acknowledge signal.
• When microprocessor
receives INTR signal, it
acknowledges the interrupt
by generating this signal.
• It is an active low signal.
ALE
Pin 25 (Output)
• It is a Write signal.
• It is used to write data in
memory or output device
depending on the status of
M/IO signal.
• It is an active low signal.
HLDA
Pin 30 (Output)
• It is a Hold Acknowledge
signal.
• It is issued after receiving the
HOLD signal.
• It is an active high signal.
HOLD
Pin 31 (Input)
S2 S1 S0 Status
0 0 0 Interrupt Acknowledge
0 0 1 I/O Read
0 1 0 I/O Write
0 1 1 Halt
1 0 0 Opcode Fetch
1 0 1 Memory Read
1 1 0 Memory Write
1 1 1 Passive
LOCK
Pin 29 (Output)
I-10
8086 Programmers Model
8086 Addressing Modes
4
8086 Addressing Modes
7
Register Addressing Mode
9
2.IMMEDIATE ADDRESSING MODE
Immediate operand is Constant data contained in an
Instruction
i.e. The source operand is a part of instruction
instade of register memory
E.g
MOV CL,02H
3.Memory Addressing
Mode
11
Memory Addressing Mode
3.1 Direct
3.2 Register Indirect
3.3 Based Indexed
3.4 Register Relative
3.5 Relative Based Indexed
Memory Addressing Mode
EFFECTIVE ADDRESS
The offset of a memory operand is called the
operand’s effective address (EA).
Is an unsiged 16 bit no. That expresses the
operands distance in byte from the begining of the
segment
8086 has Base register and Index register
So EU calculates EA by summing a Displacement,
Content of Base register and Content of Index
register.
Memory Addressing Mode
Displacement is an 8 or 16 bit no
It is generally derived from the position of
operand name.
It’s value is constant.
Pogrammer may specify either BX or BP is to be
used as Base Register
Similarly either SI od DI may be specified as Index
Register
Memory Addressing Mode
15
Memory Addressing Mode
17
Memory Addressing Mode
19
Memory Addressing Mode
21
Memory Addressing Mode
23
Memory Addressing Mode
POP Des:
It pops the operand from top of stack to Des.
Des can be a general purpose register, segment register
(except CS) or memory location.
E.g.: POP AX
Data Transfer Instructions
• XCHG Des, Src:
– This instruction exchanges Src with Des.
– It cannot exchange two memory locations directly.
– E.g.: XCHG DX, AX
Data Transfer Instructions
• IN Accumulator, Port Address:
– It transfers the operand from specified port to accumulator
register.
• SAHF:
– It copies the contents of AH to lower byte of flag register.
• PUSHF:
– Pushes flag register to top of stack.
• POPF:
– Pops the stack top to flag register.
Arithmetic Instructions
• ADD Des, Src:
– It adds a byte to byte or a word to word.
– It effects AF, CF, OF, PF, SF, ZF flags.
– E.g.:
• ADD AL, 74H
• ADD DX, AX
• ADD AX, [BX]
Arithmetic Instructions
• ADC Des, Src:
– It adds the two operands with CF.
– It effects AF, CF, OF, PF, SF, ZF flags.
– E.g.:
• ADC AL, 74H
• ADC DX, AX
• ADC AX, [BX]
Arithmetic Instructions
• SUB Des, Src:
– It subtracts a byte from byte or a word from word.
– It effects AF, CF, OF, PF, SF, ZF flags.
– For subtraction, CF acts as borrow flag.
– E.g.:
• SUB AL, 74H
• SUB DX, AX
• SUB AX, [BX]
Arithmetic Instructions
• SBB Des, Src:
– It subtracts the two operands and also the borrow
from the result.
– It effects AF, CF, OF, PF, SF, ZF flags.
– E.g.:
• SBB AL, 74H
• SBB DX, AX
• SBB AX, [BX]
Arithmetic Instructions
• INC Src:
– It increments the byte or word by one.
– The operand can be a register or memory
location.
– It effects AF, OF, PF, SF, ZF flags.
– CF is not effected.
– E.g.: INC AX
Arithmetic Instructions
• DEC Src:
– It decrements the byte or word by one.
– The operand can be a register or memory
location.
– It effects AF, OF, PF, SF, ZF flags.
– CF is not effected.
– E.g.: DEC AX
Arithmetic Instructions
• AAA (ASCII Adjust after Addition):
– The data entered from the terminal is in ASCII format.
– In ASCII, 0 – 9 are represented by 30H – 39H.
– This instruction allows us to add the ASCII codes.
– This instruction does not have any operand.
• Other ASCII Instructions:
– AAS (ASCII Adjust after Subtraction)
– AAM (ASCII Adjust after Multiplication)
– AAD (ASCII Adjust Before Division)
Arithmetic Instructions
• DAA (Decimal Adjust after Addition)
– It is used to make sure that the result of adding two
BCD numbers is adjusted to be a correct BCD number.
– It only works on AL register.
• DAS (Decimal Adjust after Subtraction)
– It is used to make sure that the result of subtracting
two BCD numbers is adjusted to be a correct BCD
number.
– It only works on AL register.
Arithmetic Instructions
• NEG Src:
– It creates 2’s complement of a given
number.
– That means, it changes the sign of a
number.
Arithmetic Instructions
• CMP Des, Src:
– It compares two specified bytes or words.
– The Src and Des can be a constant, register or memory
location.
– Both operands cannot be a memory location at the
same time.
– The comparison is done simply by internally
subtracting the source from destination.
– The value of source and destination does not change,
but the flags are modified to indicate the result.
Arithmetic Instructions
• MUL Src:
– It is an unsigned multiplication instruction.
– It multiplies two bytes to produce a word or two words to
produce a double word.
– AX = AL * Src
– DX : AX = AX * Src
– This instruction assumes one of the operand in AL or AX.
– Src can be a register or memory location.
• IMUL Src:
– It is a signed multiplication instruction.
Arithmetic Instructions
• DIV Src:
– It is an unsigned division instruction.
– It divides word by byte or double word by word.
– The operand is stored in AX, divisor is Src and the
result is stored as:
• AH = remainder AL = quotient
• IDIV Src:
– It is a signed division instruction.
Arithmetic Instructions
• CBW (Convert Byte to Word):
– This instruction converts byte in AL to word in AX.
– The conversion is done by extending the sign bit of AL
throughout AH.
• CWD (Convert Word to Double Word):
– This instruction converts word in AX to double word in
DX : AX.
– The conversion is done by extending the sign bit of AX
throughout DX.
Bit Manipulation Instructions
• These instructions are used at the bit level.
• These instructions can be used for:
– Testing a zero bit
– Set or reset a bit
– Shift bits across registers
Bit Manipulation Instructions
• NOT Src:
– It complements each bit of Src to produce 1’s
complement of the specified operand.
– The operand can be a register or memory
location.
Bit Manipulation Instructions
• AND Des, Src:
– It performs AND operation of Des and Src.
– Src can be immediate number, register or memory
location.
– Des can be register or memory location.
– Both operands cannot be memory locations at the
same time.
– CF and OF become zero after the operation.
– PF, SF and ZF are updated.
Bit Manipulation Instructions
• OR Des, Src:
– It performs OR operation of Des and Src.
– Src can be immediate number, register or memory
location.
– Des can be register or memory location.
– Both operands cannot be memory locations at the
same time.
– CF and OF become zero after the operation.
– PF, SF and ZF are updated.
Bit Manipulation Instructions
• XOR Des, Src:
– It performs XOR operation of Des and Src.
– Src can be immediate number, register or memory
location.
– Des can be register or memory location.
– Both operands cannot be memory locations at the
same time.
– CF and OF become zero after the operation.
– PF, SF and ZF are updated.
Bit Manipulation Instructions
• SHL Des, Count:
– It shift bits of byte or word left, by count.
– It puts zero(s) in LSBs.
– MSB is shifted into carry flag.
– If the number of bits desired to be shifted is 1, then
the immediate number 1 can be written in Count.
– However, if the number of bits to be shifted is more
than 1, then the count is put in CL register.
Bit Manipulation Instructions
• SHR Des, Count:
– It shift bits of byte or word right, by count.
– It puts zero(s) in MSBs.
– LSB is shifted into carry flag.
– If the number of bits desired to be shifted is 1, then
the immediate number 1 can be written in Count.
– However, if the number of bits to be shifted is more
than 1, then the count is put in CL register.
Bit Manipulation Instructions
• ROL Des, Count:
– It rotates bits of byte or word left, by count.
– MSB is transferred to LSB and also to CF.
– If the number of bits desired to be shifted is 1,
then the immediate number 1 can be written in
Count.
– However, if the number of bits to be shifted is
more than 1, then the count is put in CL register.
Bit Manipulation Instructions
• ROR Des, Count:
– It rotates bits of byte or word right, by count.
– LSB is transferred to MSB and also to CF.
– If the number of bits desired to be shifted is 1,
then the immediate number 1 can be written in
Count.
– However, if the number of bits to be shifted is
more than 1, then the count is put in CL register.
Program Execution Transfer Instructions
• These instructions cause change in the
sequence of the execution of instruction.
• This change can be through a condition or
sometimes unconditional.
• The conditions are represented by flags.
Program Execution Transfer Instructions
• CALL Des:
– This instruction is used to call a subroutine or function
or procedure.
– The address of next instruction after CALL is saved
onto stack.
• RET:
– It returns the control from procedure to calling
program.
– Every CALL instruction should have a RET.
Program Execution Transfer Instructions
• JMP Des:
– This instruction is used for unconditional jump
from one place to another.
• SCAS String:
– It scans a string.
– It compares the String with byte in AL or with
word in AX.
String Instructions
• MOVS / MOVSB / MOVSW:
– It causes moving of byte or word from one string
to another.
– In this instruction, the source string is in Data
Segment and destination string is in Extra
Segment.
– SI and DI store the offset values for source and
destination index.
String Instructions
• REP (Repeat):
– This is an instruction prefix.
– It causes the repetition of the instruction until CX
becomes zero.
– E.g.: REP MOVSB STR1, STR2
• It copies byte by byte contents.
• REP repeats the operation MOVSB until CX becomes
zero.
String Instructions
String is a collection of bytes, words, or long-words that can be up to 64KB
in length
String instructions can have at most two operands. One is referred to as source
string and the other one is called destination string
— Source string must locate in Data Segment and SI register points to the current
element of the source string
— Destination string must locate in Extra Segment and DI register points to the current
element of the destination string
DS : SI ES : DI
0510:0000 53 S 02A8:2000 53 S
0510:0001 48 H 02A8:2001 48 H
0510:0002 4F O 02A8:2002 4F O
0510:0003 50 02A8:2003 50
P P
0510:0004 50 P 02A8:2004 50 P
0510:0005 45 E 02A8:2005 49 I
0510:0006 52 R 02A8:2006 4E N
Source String Destination String
Repeat Prefix Instructions
REP String Instruction
— The prefix instruction makes the microprocessor repeatedly execute the string instruction
until CX decrements to 0 (During the execution, CX is decreased by one when the string
instruction is executed one time).
— For Example:
MOV CX, 5
REP MOVSB
By the above two instructions, the microprocessor will execute MOVSB 5 times.
DS : SI ES : DI
MOV AX, 0510H 0510:0000 53 S 0300:0100
MOV DS, AX 0510:0001 48 H
MOV SI, 0 4F
0510:0002 O
MOVAX, 0300H
0510:0003 50
MOV ES, AX P
MOV DI, 100H 0510:0004 50 P
CLD 0510:0005 45 E
MOV CX, 5 52
0510:0006 R
REP MOVSB
Source String Destination String
String Instructions
CMPSB (CMPSW)
— Compare bytes (words) at memory locations DS:SI and ES:DI;
update SI and DI according to DF and the width of the data being compared
— It modifies flags
—Example:
Assume: ES = 02A8H DS : SI
DI = 2000H ES : DI
0510:0000 53 S 53 S
DS = 0510H 02A8:2000
SI = 0000H 0510:0001 48 H 48 H
02A8:2001
0510:0002 4F O 4F O
02A8:2002
CLD 0510:0003 50
P 50
02A8:2003 P
MOV CX, 9 50 P P
0510:0004 02A8:2004 50
REPZ CMPSB 45
0510:0005 E 49 I
02A8:2005
0510:0006 52 R 4E N
02A8:2006
What’s the values of CX after
The execution? Source String Destination String
String Instructions
SCASB (SCASW)
SCASB compares the byte in AL with the byte
at [ES:DI] or [ES:EDI], and sets the flags accordingly. It
then increments or decrements (depending on the
direction flag: increments if the flag is clear, decrements
if it is set) DI (or EDI).
SCASW and SCASD work in the same way, but they
compare a word to AX or a doubleword to EAX instead of
a byte to AL, and increment or decrement the
addressing registers by 2 or 4 instead of 1.
LODSB (LODSW)
— Load byte (word) at memory location DS:SI to AL (AX);
update SI according to DF and the width of the data being transferred
— It does not modify flags
STOSB (STOSW)
— Store byte (word) at in AL (AX) to memory location ES:DI;
update DI according to DF and the width of the data being transferred
— It does not modify flags
Processor Control Instructions
• These instructions control the processor itself.
• 8086 allows to control certain control flags
that:
– causes the processing in a certain direction
– processor synchronization if more than one
microprocessor attached.
Processor Control Instructions
• STC:
– It sets the carry flag to 1.
• CLC:
– It clears the carry flag to 0.
• CMC:
– It complements the carry flag.
Processor Control Instructions
• STD:
– It sets the direction flag to 1.
– If it is set, string bytes are accessed from higher
memory address to lower memory address.
• CLD:
– It clears the direction flag to 0.
– If it is reset, the string bytes are accessed from lower
memory address to higher memory address.
Addressing Modes
Exceptions
String addressing
Port addressing (e.g. IN AL, 79H)
Machine Cycles
• Also Bus Cycles
• Definition:
– One discrete information transfer on the buses.
By micropro
100 ns
INTR
A0-A15,A16/S3 – A19/S6
INTA
Interrupt Address / data bus
interface
TEST
D0 – D15
NMI
8086
RESET ALE
MPU
BHE / S7
M / IO Memory
DMA HOLD I/O controls
DT / R
interface
HLDA RD
WR
Vcc
DEN
Mode select
READY
MN / MX
CLK clock
M. Krishna Kumar
Minimum Mode 8086 MPU
Block Diagram of theMM/M1/LU3/V1/2004 20
Minimum Mode Interface:
When the Minimum mode operation is selected, the 8086 provides
all control signals needed to implement the memory and I/O
interface.
• The signal read RD and write WR indicates that a read
cycle or a write bus cycle is in progress. The 8086 switches
bus
WR to logic 0 to signal external device that valid write or
output data are on the bus.
• On the other hand, RD indicates that the 8086 is
performing a read of data of the bus. During read
operations, one other control signal is also supplied. This
is
DEN ( data enable) and it signals external devices when
• they should put data on the bus.
There is one other control signal that is involved with
the memory and I/O interface. This is the READY
signal.
M. Krishna Kumar MM/M1/LU3/V1/2004 26
ALE
Pin 25 (Output)
0 0 1 I / O read
1 0 I/O write
0
1 0 1 Memory read
1 1 0 Memory write
BHE S7 – S3
ADD / STATUS A19 – A16
Bus reserved
ADD / DATA A15 – A0 for data in D15 – D0
RD
DEN
DT / R
Clk
ALE
BHE S7 – S3
ADD / STATUS A19 – A16
WR
DEN
DT / R
Figure 9–21 The 8288 bus controller; (a) block diagram and (b) pin-out.
8288 Bus Controller Pin Functions
S2, S1, and S0
• Status inputs are connected to the status output
pins on 8086/8088.
– three signals decoded to generate timing signals
CLK
• The clock input provides internal timing.
– must be connected to the CLK output pin of
the 8284A clock generator
8288 Bus Controller Pin Functions
ALE
• The address latch enable output is used to
demultiplex the address/data bus.
DEN
• The data bus enable pin controls the bidirectional
data bus buffers in the system.
DT/R
• Data transmit/receive signal output to control
direction of the bidirectional data bus buffers.
8288 Bus Controller Pin Functions
AEN
• The address enable input causes the 8288 to
enable the memory control signals.
CEN
• The control enable input enables the command
output pins on the 8288.
IOB
• The I/O bus mode input selects either I/O
bus mode or system bus mode operation.
8288 Bus Controller Pin Functions
AIOWC
• Advanced I/O write is a command output to an
advanced I/O write control signal.
IORC
• The I/O read command output provides
I/O with its read control signal.
IOWC
• The I/O write command output provides I/O with
its main write signal.
8288 Pin Functions
AMWT
• Advanced memory write control pin provides
memory with an early/advanced write signal.
MWTC
• The memory write control pin provides memory
with its normal write control signal.
MRDC
• The memory read control pin provides memory
with a read control signal.
8288 Bus Controller Pin Functions
INTA
• The interrupt acknowledge output acknowledges
an interrupt request input applied to the INTR pin.
MCE/PDEN
• The master cascade/peripheral data output
selects cascade operation for an interrupt
controller if IOB is grounded, and enables the I/O
bus transceivers if IOB is tied high.
Maximum Mode Interface (cont..)
Status Inputs
CPU Cycles 8288
S2 S1 S0 Command
0 0 0 Interrupt Acknowledge INTA
0 0 1 Read I/O Port IORC
0 1 0 Write I/O Port IOWC, AIOWC
0 1 1 Halt None
1 0 0 Instruction Fetch MRDC
1 0 1 Read Memory MRDC
1 1 0 Write Memory MWTC, AMWC
1 1 Passive None
1
Clk
AL
E
S2 – S0 Active Inactive Active
MRDC
DT / R
DEN
Clk
ALE
ADD/STATUS BHE S7 – S3
DT / R high
DEN
Clk
RQ / GT
Assembler Compiler
Linker
Machine Code
Assembler Directives: Introduction
• TRAP
• RST 7.5
• RST6.5
• RST5.5
• INTR