The ARM Architecture

T H E A R C H I T E C T U R E F O R T
TM H E D I G I T A L W O R1 L D
 Agenda

 Introduction to ARM Ltd

Programmers Model
Instruction Set
System Design
Development Tools

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 ARM Ltd
 Founded in November 1990
 Spun out of Acorn Computers

 Designs the ARM range of RISC processor

cores
 Licenses ARM core designs to semiconductor
partners who fabricate and sell to their
customers.
 ARM does not fabricate silicon itself

 Also develop technologies to assist with the

design-in of the ARM architecture
 Software tools, boards, debug hardware,
application software, bus architectures,
peripherals etc

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 ARM Versions
 ARM Architecture versions and products
 Key architecture revisions and products:
 ARMv1-ARMv3: largely lost in the mists of time
 ARMv4T: ARM7TDMI – first Thumb processor
 ARMv5TEJ(+VFPv2): ARM926EJ-S
 ARMv6K(+VFPv2): ARM1136JF-S, ARM1176JFZ-S,
 ARM11MPCore – first
Multiprocessing Core
 ARMv7-A+VFPv3: Cortex-A8
 ARMv7-A+MPE+VFPv3: Cortex-A5, Cortex-A9
 ARMv7-A+MPE+VE+LPAE+VFPv4: Cortex-A15
 ARMv7-R: Cortex-R4, Cortex-R5
 ARMv6-M: Cortex–M0
 ARMv7-M: Cortex-M3, Cortex-M4
 The ARM7TDMI (ARM7+16 bit Thumb+JTAG Debug+fast Multiplier+enhanced ICE)
processor implements the ARMv4 instruction set. The ARM7TDMI-S variant is the
Synthesizable core

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 ARM Powered Products

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 ARM 7 Features

 32 bit Microcontroller
 32 bit ALU
 32 bit data bus
 32 bit Instruction Set(RISC)
 32 bit address bus(4 GB memory)
 Von Neumann Model(common data memory and programme memory)
 3 stage pipeline(f,d,e)
 37 registers each(available r0-r15 at a time, 31 gpr,6 status registers)
 Load-Store model
 7 operating modes and 7 interrupts and exceptions
 7 addressing modes
 3 data formats(8,16,32 bit formats)

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ARM Architecture:-

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 Pipeline Organization (2)

 3-stage pipeline: Fetch – Decode - Execute

 Three-cycle latency,
one instruction per cycle throughput
i
n
s
t i
r Fetch Decode Execute
u
c
t i+1 Fetch Decode Execute
i
o
n i+2 Fetch Decode Execute
cycl
e

t t+1 t+2 t+3 8 t+4

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 MEMORY ORGANIZATION
Word, half-word
alignment (xxxx00 or
xxxxx0)
ARM can be set up to
access data in either
little-endian
or big-endian format,
through they default to
little-endian.

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 Data Sizes and Instruction Sets

 The ARM is a 32-bit architecture.

 When used in relation to the ARM:

 Byte means 8 bits
 Halfword means 16 bits (two bytes)
 Word means 32 bits (four bytes)

 Most ARM’s implement two instruction sets

 32-bit ARM Instruction Set
 16-bit Thumb Instruction Set

 Jazelle cores can also execute Java bytecode

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 Operating Modes

 Seven operating modes:

 User
 Privileged:
 System (version 4 and above)
 FIQ
 IRQ
 Abort
exception modes
 Undefined
 Supervisor

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 Processor Modes
 The ARM has seven basic operating modes:
 User : non-privileged mode under which most tasks run(programs and
applications)

 FIQ : entered when a high priority (fast) interrupt is raised

 IRQ : entered when a low priority (normal) interrupt is raised

 Supervisor : entered on reset (operating system kernal operates in) and when
a Software Interrupt instruction is executed

 Abort : used to handle memory access violations

 Undef : used to handle undefined instructions or not supported by the

implementations .

 System : privileged mode using the same registers as user mode that allows
full read- write access to cpsr.

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 The Registers

 ARM has 37 registers all of which are 32-bits long.

 1 dedicated program counter
 1 dedicated current program status register
 5 dedicated saved program status registers
 30 general purpose registers

 The current processor mode governs which of several banks is

accessible. Each mode can access
 a particular set of r0-r12 registers
 a particular r13 (the stack pointer, sp) and r14 (the link register, lr)
 the program counter, r15 (pc)
 the current program status register, cpsr

Privileged modes (except System) can also access

 a particular spsr (saved program status register)

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 The ARM Register Set

Current Visible Registers

r0
Abort
Undef
SVC
IRQ
FIQ
User Mode
Mode
Mode
Mode
Mode r1
r2
r3 Banked out Registers
r4
r5 FIQ
r6 User
User (10001)
FIQ IRQ
IRQ SVC
Superv Undef Abort
r7 (10000) (10010) -isor (11011)
r8 r8 r8 (10011)
r9 r9 r9
r10 r10 r10
r11 r11 r11
r12 r12 r12
r13 (sp) r13 (sp) r13 (sp) r13 (sp) r13 (sp) r13 (sp) r13 (sp)
r14 (lr) r14 (lr) r14 (lr) r14 (lr) r14 (lr) r14 (lr) r14 (lr)
r15 (pc)

cpsr
spsr spsr spsr spsr spsr spsr

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 Register Organization Summary
User FIQ IRQ SVC Undef Abort
r0
r1
User
r2 mode
r3 r0-r7,
r4 r15, User User User User
and mode mode mode mode Thumb state
r5
cpsr r0-r12, r0-r12, r0-r12, r0-r12, Low registers
r6
r15, r15, r15, r15,
r7 and and and and
r8 r8 cpsr cpsr cpsr cpsr
r9 r9
r10 r10 Thumb state
r11 r11 High registers
r12 r12
r13 (sp) r13 (sp) r13 (sp) r13 (sp) r13 (sp) r13 (sp)
r14 (lr) r14 (lr) r14 (lr) r14 (lr) r14 (lr) r14 (lr)
r15 (pc)

cpsr
spsr spsr spsr spsr spsr

Note: System mode uses the User mode register set

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 Program Status Registers
31 28 27 24 23 16 15 8 7 6 5 4 0

N Z C V Q J U n d e f i n e d I F T mode
f s x c
 Condition code flags  Interrupt Disable bits.
 N = Negative result from ALU  I = 1: Disables the IRQ.
 Z = Zero result from ALU  F = 1: Disables the FIQ.
 C = ALU operation Carried out
 V = ALU operation oVerflowed
 T Bit
 Architecture xT only
 T = 0: Processor in ARM state
 Sticky Overflow flag - Q flag
 T = 1: Processor in Thumb state
 Architecture 5TE/J only
 Indicates if saturation has occurred
 Mode bits
 Specify the processor mode
 J bit
 Architecture 5TEJ only
 J = 1: Processor in Jazelle state
(JAVA execution)

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 Program Counter (r15)

 When the processor is executing in ARM state:

 All instructions are 32 bits wide
 All instructions must be word aligned
 Therefore the pc value is stored in bits [31:2] with bits [1:0] undefined (as
instruction cannot be halfword or byte aligned).

 When the processor is executing in Thumb state:

 All instructions are 16 bits wide
 All instructions must be halfword aligned
 Therefore the pc value is stored in bits [31:1] with bit [0] undefined (as
instruction cannot be byte aligned).

 When the processor is executing in Jazelle state:

 All instructions are 8 bits wide
 Processor performs a word access to read 4 instructions at once

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 Exception Handling

 When an exception occurs, the ARM:

 Copies CPSR into SPSR_<mode>
 Sets appropriate CPSR bits
 Change to ARM state 0x1C FIQ
 Change to exception mode
0x18 IRQ
 Disable interrupts (if appropriate)
0x14 (Reserved)
 Stores the return address in LR_<mode>
 Sets PC to vector address 0x10 Data Abort
0x0C Prefetch Abort
 To return, exception handler needs to: 0x08 Software Interrupt
 Restore CPSR from SPSR_<mode>
0x04 Undefined Instruction
 Restore PC from LR_<mode>
0x00 Reset
This can only be done in ARM state.
Vector Table
Vector table can be at
0xFFFF0000 on ARM720T
and on ARM9/10 family devices

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The only exception possible in kernel mode is the page fault.

 Interrupts and exceptions both alter the program flow.

Interrupts are used to handle external events (serial ports, keyboard) and

exceptions are used to handle instruction faults, (division by zero, undefined opcode).

Priority order – Reset (highest priority)

– Data abort
– FIQ
– IRQ
– Prefetch abort
– SWI, undefined instructio

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 Reset vector- location of the first instruction executed by the processor when
power is applied.
Undefined- used when the processor cannot decode an instruction.
Software- used when SWI instruction executed in the program.
Prefetch abort vector – used the processor attempts to fetch an instruction form
an address without the correct access permission.
Data abort vector- it is raised when an instruction attempts access data memory
without the correct access permissions
Interrupt request vector- used by external hardware to interrupt the normal
execution flow of the processor.
Fast interrupt request vector- it is reserved for hardware requiring faster
response times
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 ARM (Advanced RISC Machines) Thumb ("T" in the core's full name
specifies Thumb. Eg: ARM7TDMI)
Needs more memory than Thumb, since all Reduced memory consumption with 16-bit insturctions
are RISC 32-bit instructions (have some 32-bit instructions too)
Totally 18 Registers: R0-R12, SP(R13), Totally 12 Registers: R1-R7, SP, LR, PC, CPSR (These
LR(R14), PC(R15), CPSR, SPSR used in 12 registers have to be used to pass data between ARM
exceptions and Thumb state)
T bit = 0 of CPSR represents ARM state T bit = 1 of CPSR represents Thumb state
Branch instruction (BX or BLX) to the Branch instruction (BX or BLX) to the address with
address with LSB set to 0 enters ARM state. LSB set to 1 enters Thumb state. (Eg: BX 0x80000001)
(Eg: BX 0x80000000)
When return from Exception, if T bit of SPSR When return from Exception, if T bit of SPSR is set to
is set to 0, returns to ARM 1, returns to Thumb
- No way (instruction) to access status or coprocessor
registers
Load and store instructions of R13 register Has stack mnemonics PUSH, POP
manipulates stack

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