ESM25 firmware(FW)

Bruce Zhang
20170605
 content

1. Power up sequence
2. First rate change context
3. Mission mode flow
4. Power gating flow
5. Slicer rotation reset
6. IQ recovery
7. FW usage limitation

© 2015 Synopsys, Inc. 2

 Power up sequence
• main sequence
o FW detects rx_reset IRQ, tx_reset IRQ, TX REQ IRQ and RX REQ IRQ.
o FW has override protection for RESET IRQ during rate change sequence and
DAC override protection during mission mode. FW override protection is used
to avoid RTL update conflict.
o After phy_reset and pg_reset, FW goes to power up or power gating sequence
for offset calibration or restore offset calibration to analog.
o When phy is in link up state, customer controls RX adaptation REQ sequence to
update adaptation result.
o RX2TX loopback function is supported to update TX DCC result from RX clock
path.
o If mission mode is enable and there’s no other IRQ actions, FW loops in mission
mode function to do fine tune of RX DCC, TX DCC, CTLE offset, VGA offset,
phase offset, data slicer offset, error slicer offset, and adaptation code update.

© 2015 Synopsys, Inc. 3

 Power up sequence
Firmware Main Function
Check tx req

No
Clean dac overide/IQ/RX_OVRD/TX_OVRD Yes
Check mpll
Yes
MPLL RECAL function
recal
Check RTN reset
No

Yes Check rx No
Check pma tx
Startup offset calibration / Power gating reset ack assertion

No Yes
No Check RX
RESET IRQ No
with Override Check pma tx
protection rate change /
mpll recal
Yes
Generate RX reset
Yes

Enable TX_RESET IRQ

Check TX No
RESET IRQ
with Override
protection Update tx DCC TX DCC recal function
Yes

Generate TX reset Disable TX_RESET IRQ

No
Check rx
reset IRQ Clean tx req IRQ
Yes

Check No
pma_rx_ack Check rx req
de-assertion
Yes

Clean RX_RESET IRQ/RX REQ IRQ/

RX_RATE_CHANGE IRQ
RX recal IRQ

Reset slicer mux

No
Yes
Update RX DCC and IQC Check pma rx
rate change

Slicer rotation reset

Release pcs rx ack de-assertion
Reset slicer mux
RX ADAPT
IRQ RX ADAPT FUNCTION
Check tx reset Enable RX RESET IRQ
IRQ
No
Yes
No Update RX DCC and IQC Check RX2TX
loopback
disable IRQ
Check No
pma_tx_ack
de-assertion Disable RX RESET IRQ Yes
Yes
TX DCC Restore sequence
Clean RX REQ IRQ
Update TX DCC
Check RX2TX
loopback
Check IQ IRQ enable IRQ
Clean TX RESET IRQ
Yes
Enable RX RESET IRQ, RX2TX
Release pcs tx ack de-assertion Slicer rotation reset loopback disable IRQ

TX DCC for RX2TX recalib

IQ margin sequence

Check TX
REQ IRQ
Yes Mission mode

Yes
Check RX
© 2015 Synopsys, Inc. 4 REQ IRQ
 Power up sequence
• FW does RTUNE calibration
o ESM25 does 8 rounds of RTUNE calibration, each round of RTUNE result is
stored into AON registers and these value is used for restore during power gating.

• FW enables MPLL calibration

o If mpllla_init_disable is asserted, mplla would not be calibrated.
o If mplllb_init_disable is asserted, mpllb would not be calibrated.

• RX power up for offset calibration

o FW does VGEN calibration, AFE calibration, slicer calibration, RX DCC
calibration, IQC calibration and SIGDET calibration.
o Depends on protocol, if protocol is data slicer path, FW does all phase RX DCC
and data RX DCC and IQC for full rate and half rate for all of them and stores
these value into AON for restore in power gating. Otherwise, FW only does
bypass RX DCC for bypass slicer calibration.
o If protocol is bypass slicer path, FW does all phase RX DCC and bypass RX DCC
and IQC for full rate and half rate for all of them and stores these value into AON
for restore in power gating. Otherwise, FW only does data RX DCC for data slicer
calibration.

© 2015 Synopsys, Inc. 5

 Power up sequence
• FW checks MPLL calibration done
o If mplla is enable, FW does mplla full rate and mplla half rate calibration.
o If mpllb is enable, FW does mpllb full rate and mpllb half rate calibration.
o After mpll calibration, FW does TX DCC calibration.

• Calibration result is restored by FW and RTL

o After power up sequence, all the calibration result should be restored into analog.
o And slicer calibration result should be stored into pma adapt block as well.

• FW releases RX ACK and TX ACK to upper level

o After phy finishes power up, and all calibration result is restored into analog.
o SIGDET and RX clock and TX clock are enabled.
o FW loops in main or mission mode for new request from upper level.

© 2015 Synopsys, Inc. 6

 Power up sequence
begin calibration
Master configure
go to P0 with FULL rate
run the RX TERMINATION calibration FSM
calibrate AFE offset: ATT, CTLE, VGA
ATT_OFF, CAL_AFE
CTLE_OFF, CAL_AFE
VGA_OFF, CAL_AFE
slicer setup calibration
SETUP_SLC_VGA, CAL_AFE, binary search
dfe
no
yes
phase RX DCC CAL: differential, common
mode
BIN: RX_DCC_Q_DF, RX_CAL_DCC
BIN: RX_DCC_Q_CM_P, RX_CAL_DCC
LIN: RX_DCC_Q_DF, RX_CAL_DCC
LIN: RX_DCC_Q_CM_P, RX_CAL_DCC
Data RX DCC CAL: differential, common mode
BIN: RX_DCC_I_DF, RX_CAL_DCC
BIN: RX_DCC_I_CM_P, RX_CAL_DCC
LIN: RX_DCC_I_DF, RX_CAL_DCC
LIN: RX_DCC_I_CM_P, RX_CAL_DCC
no
dfe
yes
data IQ 90 degree calibration
CAL_IQI, CAL_IQC, linear search
Store RX DCC and IQC result into AON
Change RX clock to half rate
© 2015 Synopsys, Inc. 7
data/error slicer offset calibration
SL_DEH, CAL_DEX, binary search
SL_DEL, CAL_DEX, binary search
SL_EE, CAL_EE, binary search
SL_DOH, CAL_DOX, binary search
SL_DOL, CAL_DOX, binary search
SL_EO, CAL_EO, binary search
yes
dfe
no
RX DCC CAL: differential, common mode
BIN: RX_DCC_B_DF, RX_CAL_DCC
BIN: RX_DCC_B_CM_P, RX_CAL_DCC
LIN: RX_DCC_B_DF, RX_CAL_DCC
LIN: RX_DCC_B_CM_P, RX_CAL_DCC
phase slicer offset calibration
SL_PE, CAL_PE, binary search
SL_PO, CAL_PO, binary search
RX DCC CAL: differential, common mode
BIN: RX_DCC_I_DF, RX_CAL_DCC
BIN: RX_DCC_I_CM_P, RX_CAL_DCC
LIN: RX_DCC_I_DF, RX_CAL_DCC
LIN: RX_DCC_I_CM_P, RX_CAL_DCC
yes
dfe
no
BYPASS IQ 90 degree calibration
CAL_IQB, CAL_IQC, linear search
Store RX DCC and IQC result into AON
Change RX clock to half rate
bypass slicer offset calibration
SL_DEB, CAL_DEX, binary search
SL_DOB, CAL_DOX, binary search
calibrate the SIGET: LFPS and HF paths
SIGDET_LF_OFF, CAL_SIGDET
MPLLA TX DCC full rate and half rate:
differential, common mode
BIN: TX_DCC_DF, TX_CAL_DCC
BIN: TX_DCC_CM_P, TX_CAL_DCC
LIN: TX_DCC_DF, TX_CAL_DCC
LIN: TX_DCC_CM_P, TX_CAL_DCC
MPLLB TX DCC full rate and half rate:
differential, common mode
BIN: TX_DCC_DF, TX_CAL_DCC
BIN: TX_DCC_CM_P, TX_CAL_DCC
LIN: TX_DCC_DF, TX_CAL_DCC
LIN: TX_DCC_CM_P, TX_CAL_DCC
end calibration
 First rate change context
• First rate change context is based on bank solution.

• Each of TX and RX has 4 banks. Each bank has its own clock setup solution
and DCC solution.

• In TX side, both MPLLA and MPLLB need to be calibrated and TX DCC is

calibrated based on MPLL result.

• In RX side, based on bank solution, each bank stores phase dcc, data dcc or
bypass dcc and IQC. All of these calibration need to be done in both full rate
and half rate.

• After first rate change, in any time of rate change or bank switching, FW does
not do calibration again. FW restores DCC, IQC result into analog based on
bank selection and RX rate.

© 2015 Synopsys, Inc. 8

 First rate change context
RAW CMN AON FW RAW LANE AON
tx_vco_a_bank_0
MPLLA_TX_DCC_FULL_DIFF
MPLLA_TX_DCC_FULL_CM
MPLLA_BANK_0 MPLLA_TX_DCC_HALF_DIFF
Check mpll recal MPLLA_TX_DCC_HALF_CM
MPLLA_DONE MPLLA_TX_DCC_DONE
interrupt
MPLLA_TUNE_VAL
Y tx_vco_a_bank_1
MPLLA_TX_DCC_FULL_DIFF
MPLLA_TX_DCC_FULL_CM
MPLLA_TX_DCC_HALF_DIFF
MPLLA_BANK_1 MPLLA_TX_DCC_HALF_CM
Y MPLLA_TX_DCC_DONE
MPLLA_DONE mplla_done check mplla
MPLLA_TUNE_VAL
done tx_vco_a_bank_2
MPLLA_TX_DCC_FULL_DIFF
MPLLA_TX_DCC_FULL_CM
N MPLLA_TX_DCC_HALF_DIFF
MPLLA_TX_DCC_HALF_CM
MPLLA_TX_DCC_DONE
MPLLA_BANK_2 Does mpllla TX
MPLLA_DONE DCC
mplla_recal_bank_sel tx_vco_a_bank_3
MPLLA_TUNE_VAL MPLLA_TX_DCC_FULL_DIFF
MPLLA_TX_DCC_FULL_CM
mplla_recal_bank_sel Update mplla TX MPLLA_TX_DCC_HALF_DIFF
MPLLA_TX_DCC_HALF_CM
DCC MPLLA_TX_DCC_DONE
MPLLA_BANK_3
MPLLA_DONE

MPLLA_TUNE_VAL
mpllb_done tx_vco_a_bank_0
check mpllb MPLLB_TX_DCC_FULL_DIFF
done MPLLB_TX_DCC_FULL_CM
MPLLB_TX_DCC_HALF_DIFF
MPLLB_TX_DCC_HALF_CM
MPLLB_TX_DCC_DONE
N
Y
MPLLB_BANK_0 Does mplllb TX tx_vco_a_bank_1
MPLLB_DONE DCC MPLLB_TX_DCC_FULL_DIFF
MPLLB_TX_DCC_FULL_CM
MPLLB_TX_DCC_HALF_DIFF
MPLLB_TUNE_VAL MPLLB_TX_DCC_HALF_CM
MPLLB_TX_DCC_DONE
Update mpllb TX
MPLLB_BANK_1 DCC tx_vco_a_bank_2
MPLLB_TX_DCC_FULL_DIFF
MPLLB_TX_DCC_FULL_CM
MPLLB_DONE MPLLB_TX_DCC_HALF_DIFF
MPLLB_TX_DCC_HALF_CM
MPLLB_TUNE_VAL remove mpll mpllb_recal_bank_sel
MPLLB_TX_DCC_DONE
recal interrupt

MPLLB_BANK_2 tx_vco_a_bank_3
mpllb_recal_bank_sel MPLLB_TX_DCC_FULL_DIFF
MPLLB_TX_DCC_FULL_CM
MPLLB_DONE MPLLB_TX_DCC_HALF_DIFF
MPLLB_TX_DCC_HALF_CM
MPLLB_TUNE_VAL MPLLB_TX_DCC_DONE

{mplla_recal_bank_sel, mpllb_recal_bank_sel, tx_rate, tx_mpll_sel}

MPLLB_BANK_3
MPLLB_DONE

MPLLB_TUNE_VAL
set pma TX DCC in rate change

© 2015 Synopsys, Inc. 9

 First rate change context
RAW LANE AON FW

rx_vco_bank_0
RX_CAL_RX_DCC_FULL_DIFF
RX_CAL_RX_DCC_FULL_CM
RX_CAL_RX_DCC_FULL_PHASE_DIFF
RX_CAL_RX_DCC_FULL_PHASE_CM rx reset or rx rate
RX_CAL_IQ_FULL
change
RX_CAL_RX_DCC_HALF_DIFF
RX_CAL_RX_DCC_HALF_CM

RX_CAL_RX_DCC_HALF_PHASE_DIFF

RX_CAL_RX_DCC_HALF_PHASE_CM
RX_CAL_IQ_HALF
check VCO done
VCO_DONE

rx_vco_bank_1 N
RX_CAL_RX_DCC_FULL_DIFF
RX_CAL_RX_DCC_FULL_CM
RX_CAL_RX_DCC_FULL_PHASE_DIFF do RX DCC Y
RX_CAL_RX_DCC_FULL_PHASE_CM rx_vco_bank_sel

RX_CAL_IQ_FULL
RX_CAL_RX_DCC_HALF_DIFF
RX_CAL_RX_DCC_HALF_CM

RX_CAL_RX_DCC_HALF_PHASE_DIFF

RX_CAL_RX_DCC_HALF_PHASE_CM
RX_CAL_IQ_HALF
VCO_DONE update RX DCC

rx_vco_bank_2
RX_CAL_RX_DCC_FULL_DIFF
RX_CAL_RX_DCC_FULL_CM
RX_CAL_RX_DCC_FULL_PHASE_DIFF
RX_CAL_RX_DCC_FULL_PHASE_CM
RX_CAL_IQ_HALF
RX_CAL_RX_DCC_HALF_DIFF
clean IRQ
RX_CAL_RX_DCC_HALF_CM

RX_CAL_RX_DCC_HALF_PHASE_DIFF

RX_CAL_RX_DCC_HALF_PHASE_CM
RX_CAL_IQ_HALF
VCO_DONE

rx_vco_bank_3
RX_CAL_RX_DCC_FULL_DIFF
RX_CAL_RX_DCC_FULL_CM
RX_CAL_RX_DCC_FULL_PHASE_DIFF
RX_CAL_RX_DCC_FULL_PHASE_CM

RX_CAL_RX_DCC_HALF_DIFF
RX_CAL_RX_DCC_HALF_CM

RX_CAL_RX_DCC_HALF_PHASE_DIFF

RX_CAL_RX_DCC_HALF_PHASE_CM
set RX DCC in rate change

VCO_DONE

© 2015 Synopsys, Inc. 10 {rx_vco_bank_sel, rx_rate, rx_dfe_bypass}

 Mission mode flow

• For fast of RX DCC, TX DCC and AFE calibration from rate change, fast loop
part is added in the beginning of mission mode
o Each round of fast loop, one code is updated for RX DCC and TX DCC
and AFE calibration.
o In first 100 loops, RX DCC and TX DCC is update to a stable state.

• After first loop portion, 1 second wait counter is valid

o New offset calibration code is updated in every 1 second.
o phase slicer calibration, data/error slicer calibration and adaptation
mission mode is update to track VT update
o mission mode FOM is updated to feedback phy status to upper level.

© 2015 Synopsys, Inc. 11

 Mission mode flow
main

Set first DCC loop counter

First_DCC_LOOP=100

mm

Enable IRQ
mpll_recal/rx_reset/rx_req/
rx_adapt/tx_reset/tx_req

N
First_DCC_LOOP=0

wait 1s

MM_RX_DCC==0

RX_DCC

Y
MM_TX_DCC==0

TX_DCC

Y
MM_AFEOC_en==0

RX AFE fine offset cancellation

Decrease first DCC loop counter

First_DCC_LOOP==First_DCC_LOOP-1

N
First_DCC_LOOP=0

Y
MM_PSOC_en==0

phase slicer offset correction

Y
MM_DSOC_en==0

data slicer offset correction

Y
MM_DFE_en==0

N
© 2015 Synopsys, Inc. 12 mission mode DFE adaptation
 Power gating flow

• FW and RTL restore analog parameters after Power Gating for quick power up
o AFE offset
o Slicer offset
o DCC offset
o IQ offset
o VGEN offset
o SIGDET offset
o MPLL tune code
o RTUNE code
o adaptation code

© 2015 Synopsys, Inc. 13

 Power gating flow
Power Disable FW restores RTL restore
Reset ON parameters parameters

powerdown P1 P1.2 P1

vgen_calib
copy
copy rx_dcc_calib

copy tx_dcc_calib
iq calib

copy offset_calib
data calib

copy mplla_calib
aon bypass calib

copy mpllb_calib
adapt code

copy rtune_calib

copy sigdet_calib

pg_reset

phystatus

© 2015 Synopsys, Inc. 14

 Slicer rotation reset
• Data slicer mission mode calibration
o Data dac offset is corrupted for interrupt and data slicer mux is replaced
by error slicer.
o FW needs to reset data slicer mux and data dac code.

• 3 conditions for slicer rotation reset

o If it is in RX reset interrupt, FW directly resets data slicer mux to normal
mapping. And data slicer dac is updated by FW.
o If it is in RX rate transition update, FW directly resets data slicer mux and
data slicer dac is updated by FW.
o In other cases, after finishing RX reset interrupt and RX REQ interrupt,
FW goes through slicer mapping step by step and sets data slicer dac into
analog. During slicer rotation, RX reset and RX rate IRQ are enabled.

© 2015 Synopsys, Inc. 15

 IQ recovery

• During adapt FOM and adapt IQ stages, IQ is overwritten by FW temporally

for new IQ position
o If RX adaptation abort interrupt happen, IQ is overwritten. FW will recover
IQ to original position.
o IQ recovery function would compare current IQ position and original IQ
code. If comparison has mismatch, FW would update IQ step by step to
original IQ before finishing RX adaptation ACK sequence.

© 2015 Synopsys, Inc. 16

 FW usage limitation
• IQ delta only supports update in bank switching
o FW only supports bank IQ concept.
o IQ delta is added at the first rate change into IQ result.
o IQ delta is not valid in the same bank until force bank recal is valid for
bank switching.

• RX force recal enable is not valid in the same bank

o If upper level wants to recal the same bank, upper level has to switch
back from other bank.
o 3 conditions for RX force recal enable.
1. rx_recal_forec_enable==1 && bank_switching==1, there’s RX DCC and IQC
recal.
2. rx_recal_force_enable == 1 && bank_switching==0 && rx_rate_change==1,
there’s RX DCC and IQC recal.
3. rx_recal_force_enable == 1 && bank_switching==0 && rx_rate_change==0,
there’s no RX DCC and IQC recal.

© 2015 Synopsys, Inc. 17

 FW usage limitation
• FW may generate RX clock glitches during rate change
o During rate change, FW does full rate and half rate calibration.
o Because there’s GLCM logic when switching stat clock.
o FW has to setup new clock first then disable old clock.
o FW can not disable RX dig clock during rate change to block RX stat
clock setup.
o RX dig clock must be correct before sending back RX ACK sequence.

• RX to TX Loopback timing
o During RX to TX loopback function, TX clock path is switched to RX clock
path for loopback function.
o FW redoes TX DCC for new clock path. It takes 100us to finish TX DCC
and internal power state transition.
o When disabling RX to TX loopback function, FW needs 50us for TX DCC
restore and internal power state transition.

© 2015 Synopsys, Inc. 18

 FW usage limitation

• MPLL recal reset

o MPLL recal is based on TX REQ sequence.
o If TX reset happens during MPLL recal sequence, MPLL calibration is
interrupted.
o All lanes must be in TX reset at the same time to disable MPLL recal.
o Because MPLL recal is shared during lanes and FW does not know which
lane is master lane to kick off MPLL recal.
o Slave lanes may always wait for master lane to finish MPLL calibration.

© 2015 Synopsys, Inc. 19