Latches, Flip-Flops

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Latches

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Latches

• S-R (Set-Reset) latch

• Gated S-R latch
• Gated D latch

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Latches

• S-R latch

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Latches

• S-R latch

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Latches

• Gated S-R latch

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Latches

• Gated D latch

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Edge-Triggered Flip-Flops

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Edge-Triggered Flip-Flops

• Edge-triggered S-R flip-flop

• Edge-triggered D flip-flop
• Edge-triggered J-K flip-flop

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Edge-Triggered Flip-Flops

• Edge-triggered S-R flip-flop

Waveforms

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Edge-Triggered Flip-Flops

• Edge-triggered
S-R flip-flop

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Edge-Triggered Flip-Flops

• Edge-triggered D flip-flop

Waveforms

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Edge-Triggered Flip-Flops

• Edge-triggered D flip-flop
Edge-Triggered Flip-Flops

• Edge-triggered J-K flip-flop

Waveforms

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Edge-Triggered Flip-Flops

• Edge-triggered J-K flip-flop

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Flip-Flop Operating Characteristics

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Flip-Flop Operating Characteristics

• Propagation delay times

• the interval of time required after an input signal has
been applied for the resulting output change to occur

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Flip-Flop Operating Characteristics

• Set-up time
• the minimum interval required for the logic levels to be
maintained constantly on the inputs (J and K, or D) prior
to the triggering edge of the clock pulse in order for the
levels to be reliably clocked into the flip-flop

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Flip-Flop Operating Characteristics

• Hold time (th)

• is the minimum interval required for the logic levels to
remain on the inputs after the triggering edge of the
clock pulse in order for the levels to be reliably clocked
into the flip-flop

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Flip-Flop Operating Characteristics

• Maximum clock frequency :

• The maximum clock frequency (fmax) is the highest rate at which a
flip-flop can be reliably triggered. At clock frequencies above the
maximum, the flip-flop would be unable torespond quickly enough,
and its operation would be impaired
• Pulse widths (tw):
• Minimum pulse widths (tW) for reliable operation are usually
specified by the manufacturerfor the clock, preset, and clear
inputs. Typically, the clock is specified by its minimum HIGH time
and its minimum LOW time
• Power dissipation
• The power dissipation of any digital circuit is the total power
consumption of the device.For example, if the flip-flop operates on
a +5 V dc source and draws 5 mA of current, the power dissipation
is
P = VCC * ICC = 5 V * 5 mA = 25 mW

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Flip-Flop Applications

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Flip-Flop Applications

• Parallel data storage

• Frequency division
• Counting

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Flip-Flop Applications

• Parallel data storage

Flip-Flop Applications

• Frequency division

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Flip-Flop Applications

• Counting

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One-Shots (Monostable multivibrator)

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One-Shots

• Nonretriggerable one-shot
• Retgriggerable one-shot

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One-Shots

• Nonretriggerable one-shot

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One-Shots

• Retgriggerable one-shot

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The 555 Timer

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The 555 Timer

• Monostable (one-shot) operation

• Astable operation

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The 555 Timer

• Monostable (one-shot) operation

tw=1.1R1C1

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The 555 Timer

• Astable operation

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