1-2 Inroduction To Communication Systems Lectures 1,2-2

MICROPROCESSOR SYSTEMS
8085 Microprocessor
The Intel ® 8085 Microprocessor
• Intel introduced its first microprocessor in 1971
• 4004 was a 4-bit microprocessor
• 8008 in the same year was an 8-bit microprocessor
• Intel in 1974 introduced 8080, an 8-bit microprocessor
having 16-bit address line
• Intel 8085 is an enhancement over 8080 having:
• Clock, control and interrupt control within CPU IC
• Two added instructions
• +5v power supply
• The generic microprocessor studied was a simplified
version of 8080/8085
• 8085 has some more registers, control lines and
features
2
• 8085 is pronounced as "eighty-eighty-five"
microprocessor. It is an 8-bit microprocessor
designed by Intel in 1977 using NMOS technology.
• It has the following configuration −
• 8-bit data bus
• 16-bit address bus, which can address upto 64KB
• A 16-bit program counter
• A 16-bit stack pointer
• Six 8-bit registers arranged in pairs: BC, DE, HL
• Requires +5V supply to operate at 3.2 MHZ single
phase clock
• It is used in washing machines, microwave ovens,
mobile phones, PART
etc.2- Microprocessor Architecture
and Programming
3
8085 Microprocessor – Functional
Units
• 8085 consists of the following functional
units −
Accumulator
• It is an 8-bit register used to perform
arithmetic, logical, I/O & LOAD/STORE
operations. It is connected to internal data
bus & ALU.
Arithmetic and logic unit
• As the name suggests, it performs
arithmetic and logical operations like
Addition, Subtraction, AND, OR, etc. on 8-
bit data. PART 2- Microprocessor Architecture
and Programming
4
General purpose register
• There are 6 general purpose registers in
8085 processor, i.e. B, C, D, E, H & L. Each
register can hold 8-bit data.
• These registers can work in pair to hold 16-
bit data and their pairing combination is like
B-C, D-E & H-L.
PART 2- Microprocessor Architecture

and Programming
5
Program counter
• It is a 16-bit register used to store the memory
address location of the next instruction to be
executed.
• Microprocessor increments the program whenever
an instruction is being executed, so that the
program counter points to the memory address of
the next instruction that is going to be executed.

and Programming
6
Stack pointer
• It is also a 16-bit register works like stack, which is
always incremented/decremented by 2 during push
& pop operations.
Temporary register
• It is an 8-bit register, which holds the temporary
data of arithmetic and logical operations.

and Programming
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Flag register
• It is an 8-bit register having five 1-bit flip-flops, which holds either 0
or 1 depending upon the result stored in the accumulator.
• These are the set of 5 flip-flops −
• Sign (S)
• Zero (Z)
• Auxiliary Carry (AC)
• Parity (P)
• Carry (C)
• Its bit position is shown in the following table −
• D7 D6 D5 D4 D3 D2 D1 D0
• S Z AC P C

and Programming
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Instruction register and decoder
• It is an 8-bit register. When an instruction is fetched
from memory then it is stored in the Instruction
register.
• Instruction decoder decodes the information
present in the Instruction register.

and Programming
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Timing and control unit
• It provides timing and control signal to the
microprocessor to perform operations.
• Following are the timing and control signals, which
control external and internal circuits −
• Control Signals: READY, RD’, WR’, ALE
• Status Signals: S0, S1, IO/M’
• DMA Signals: HOLD, HLDA
• RESET Signals: RESET IN, RESET OUT

and Programming
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Interrupt control
• As the name suggests it controls the
interrupts during a process. When a
microprocessor is executing a main program
and whenever an interrupt occurs, the
microprocessor shifts the control from the
main program to process the incoming
request. After the request is completed, the
control goes back to the main program.
• There are 5 interrupt signals in 8085
microprocessor: INTR, RST 7.5, RST 6.5,
RST 5.5, TRAP.

and Programming
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Serial Input/output control
• It controls the serial data communication by using
these two instructions: SID (Serial input data) and
SOD (Serial output data).

and Programming
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Address buffer and address-data buffer
• The content stored in the stack pointer and
program counter is loaded into the address buffer
and address-data buffer to communicate with the
CPU.

and Programming
13
Address bus and data bus
• Data bus carries the data to be stored. It is
bidirectional, whereas address bus carries the
location to where it should be stored and it is
unidirectional. It is used to transfer the data &
Address I/O devices.
• The memory and I/O chips are connected to these
buses; the CPU can exchange the desired data
with the memory and I/O chips.

and Programming
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Computer Systems Engineering, QUEST, Nawabshah
13CS
15
PC A
1000
D
IR 1000 1st
1001 2nd
C 1002 3rd
ID
RD

and Programming
16
13CS
17
13CS
18
• Adding two numbers,
• C language
• int a,b,c;
• a = 1;
B = 2;
c = a+b;
• Operands, operation, result (where to

store)
• 3+2=5
• A <-ADD A, B
• ADD B 8085
• AA + B

and Programming
19
• ADD B • SUB B A<- A-B
• ADD C
• SUB C
• ADD D • SUB D
• Accumulated net result

will be in A
(Accumulator)

and Programming
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Stack is a structured data structure .
It takes only takes one address to locate any item

inside a stack which can be used to implement all
addresses.
Stack pointer stores the address of the top of stack,
or the address of the top element in the stack.
Queue takes two addresses, last element, and first

element.

and Programming
21
D
1000 1000 4
1001 3
1002 2
Value of the TOS : ?

Address of the TOS:?
SP: ?

and Programming
22
Electrical Engineering, QUEST, Nawabshah. 14EL
The Intel ® 8085 Pin Diagram and

Functions
• It’s a 40-pin DIP
• Due to less pins available, the data bus is multiplexed
with lower address lines (AD0-AD7)
• To multiplex means first select one and then select other
• MPU first uses these lines as lower byte of address and
then send/receive data on theses lines
• To inform peripherals about address/data, MPU uses a
control signal Address Latch Enable (30)
• Address / Data lines may be tri-state
• Power pins (20, 40)
• Clock circuitry (1,2)
31 May 2019
and Programming
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23
8085 Pin Diagram (Fig.)
24

Functions (Contd.)
• When RESETIN* (36) goes low, PC resets to 0000h
• RD* and WR* are same as of generic microprocessor
• RESETOUT (3) is a signal to peripherals that it is being reset
• CLK (37)
• INTR (10) can be enabled / disabled by software
• Beside the regular INTR, 8085 has four other interrupt inputs
• TRAP (causes MPU to jump to a routine at specific address)
• RST 7.5 (causes MPU to jump to a routine at specific address)
• INTR being at the lowest priority interrupt
• When INTR is received, the MPU sends INTA* signal to the
device and device then sends a code which decides the address
to jump at
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and Programming
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25

Functions (Contd.)
• SOD, SID (4,5)
• Serial output data and Serial Input data
• SID loads 1 bit into MSB of Accumulator with RIM instruction
• SOD is set/reset by the MPU SIM instruction
• READY input (35)
• Comes from the peripheral device indicating that it is ready
to send / receive the data
• If this is LOW, MPU can wait or it can proceed with read /
write tasks
• It is used when slow devices communicate with the MPU
• HOLD input (39) and HLDA output (37)
• Used when a device wants to use DMA
• MPU sends HLDAPART
and2- Microprocessor
relieves control
Architecture
over Buses and
31 May 2019 26
control signals and Programming
26

Functions (Contd.)
• IO/M* output (34)
• Control signal to indicate from where read / write
operations is being done (I/O or memory)
• S0 and S1 outputs (29,33)
• Used to select one of the machine cycle
8085 Control Signals
Machine Cycle Status
I/O M* S1 S0
0 0 1 Memory Write
0 1 0 Memory Read
1 0 1 I/O Write
1 1 0 I/O Read
0 1 1 Opcode Fetch
1 1 1 Interrupt acknowledge
* 0 0 Halt
* XPARTX 2- Microprocessor
Hold Architecture
and Programming
* X X Reset 27
Interrupts & Interrupt handler

addresses
Name Priority Address Branched to when interrupt occurs
TRAP 1 24h
RST7.5 2 3Ch
RST6.5 3 34h
RST5.5 4 2Ch
INTR 5 (1)*
(1)* Depends upon the number provided by the 8259 or other circuitry to the MPU
when interrupt is acknowledged.

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and Programming
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28
Addressing Modes
• “The manner in which operand is given in an
instruction.” We need address of the data when we
perform any operation or any instruction.
• 8085 uses 5 addressing modes
• Implied
• No register or memory location involved. Like STC, NOP, HLT
• Register
• Both operands are in MPU registers like ADD C
• Immediate
• Data immediately follows in the next byte to op code (MVI)
• Direct
• 3-byte instructions. 1st byte op code. Next 2 bytes address like
LDA
• Register Indirect
• Uses register pair to address memory like ADD M
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and Programming
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29
Addressing Modes
• Different ways by which a MPU can access data.
• The way the operands are chosen during execution
of an inst is determined by the addressing modes.
Immediate:
• Register:
Direct:
• Indirect:
• Implied/implicit

and Programming
30
• Immediate addressing mode: (Data itself is present in
the instruction) (memory)
• 8 or 16 bit data can be specified as a part of instruction.

(Operand)
• Eg:
MVI B 36H --------- 36H is copied into B register from memory

Move Immediate 36H (data) into B register

and Programming
31
• Direct Addressing Mode: (Address of the data is present
in the instruction) (memory)
• Eg,
LDA 6000H
Load accumulator with data in memory at address
6000H)
Accumulator
6000H 77
77
6001H 88
6002H 89
and Programming
32
• Indirect Addressing Mode: (Address of the data is
present as content of another register pair.)
(memory)
EG;
LDAX D
Load Accumulator with data in memory location/addreess
whose address is present in register pair (X). (DE in this
case)
6000H 89
D E 6001H 78
60 02 6002H 61 Accumulator
6003H 56
and Programming
• Register Addressing Mode: (Moving data from one
register to another, data is transferred between registers
not from memory)
(Register)
EG;
MOV B, C
Move contents or data in C register to B
MOV D, E

and Programming
34
• Implicit Addressing Mode: (Only opcode- addressing will
be internally performed in the register or single register)
In implicit addressing mode no data or operand is
present in the instruction and some operation is
performed by the instruction.
EG; CMA ----- complement data or content present

in accumulator

and Programming
35
8085 Instruction Set

• Intel 8085 uses stored program concepts
• Programs are stored in Program Memory
• Data are stored in Data memory
• In program memory the program is stored as:
• Sequence of 1,2 or 3-byte instructions
• The first byte of instruction is always the op-code
• The next byte (s) if present specifies the operands
• Op-code + data are in binary form
• Op-codes are fixed by the manufacturers in the design of
chip
• The set of instructions (op-codes) along with some additional
information is called Instruction Set of microprocessor
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and Programming
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36
8085 Instruction Set (Contd.)

• Intel ® 8085 instruction set is divided into following
group
• Data Transfer Group
• Moves data between register and register - memory
• Arithmetic Group
• Addition, Subtraction, Increment, Decrement register and
memory
• Logical and bit manipulation Group
• Performs Logical AND, OR, XOR, Comparison, Rotation,
complement
• Branch Group
• Conditional and un conditional Jumps, Call and return
• Stack, I/O and M/C Control Group
31 May 2019
and Programming
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37

• Intel ® 8085 instruction set
• 74 operation codes, eg; MOV MVI etc
• A total of 246 instructions can be executed by 8085, eg;
MOV A, B MVI A, 03 etc

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and Programming
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38

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and Programming
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39

31 May 2019
and Programming
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40
Data Transfer Instructions

• Includes:
• Data transfer from register to register
• Data transfer from register to memory
• Data transfer from memory to register
• Moving immediate number into register
• Destination and Source operands
• No Flag register will be altered

31 May 2019
and Programming
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41
• MOV r1, r2 (Register)

• MOV M, r (Register Indirect)
• MOV r, M (Register Indirect)
• MVI r, data (Immediate)
• MVI M, data (Immediate / Register Indirect)
• LXI rp, data16 (Immediate)
• LDA addr (Direct)
• STA addr (Direct)
• LHLD addr (Direct)
• SHLD addr (Direct)
• LDAX rp (Register Indirect)
• STAX rp (Register Indirect)
31 May 2019
and Programming
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Examples:
• Operation/description • Instruction
• Move 8-bit no: 4F in reg B • MVI B, 4FH

• Copy from reg B to Reg A • MOV B
• Load 16-bit number:2050 • LXI H,2050H
in reg pair HL
• Copy from reg B to • MOV M, B (M specifies
Memory Address 2050 the address in memory)
• OUT 01H O/P ACC

• IN 07H ACC I/P
• Copy between I/O to acc

and Programming
43
Arithmetic Instructions
• Add r (Register)
• Add M (Register Indirect)
• ADI data (Immediate)
• ADC r (Register)
• ADC M (Register Indirect)
• ACI data (Immediate)
• SUB r (Register)
• SUB M (Register Indirect)
• SUI data (Immediate)
44
Examples
• Description • Instruction
• Add 8bit no 32H to ACC • ADI 32H

• Add content of reg B to ACC • ADD B
• Sub 8bit no 32H from Acc • SUI 32H
• Sub contect of reg C from ACC • SUB C
• Inc the content of reg D by 1

• INR A
• Dec the content of reg B by a • DEC E

and Programming
45
• Addition and Subtraction operations affects all flags
• Increment and Decrement operations affect all flags
except carry (INX and DCX affect none)
• DAD affects only carry flag

31 May 2019
and Programming
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46
Logical and bit manipulation

Instructions
• ANA r (Register) • ORI data (Immediate)
• ANA M (Register Indirect) • CMP r (Register)
• ANI data (Immediate) • CMP M (Register Indirect)
• XRA r (Register) • CPI data (Immediate)
• XRA M (Register Indirect) • RLC
• XRI data (Immediate) • RRC
• ORA r (Register) • RAL
• ORA M (Register Indirect) • RAR
• CMA
• CMC
• STC
31 May 2019
and Programming
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47
Logical and bit manipulation
Instructions
Examples
• Logically AND reg H with ACC • ANA H

• Logically OR reg L with ACC • ORA L
• Logically XOR reg B with Acc • XRA B
• Compare contents of reg c • CMP C
with ACC
• Compliment ACC • CMA
• Roate ACC left • RAL

and Programming
48
Branch Instructions
• JMP addr (Immediate)
• Jcondition addr (Immediate)
• CALL addr (Immediate)
• Ccondition addr (Immediate/ Register Indirect)
• RET (Register Indirect)
• Rcondition (Register Indirect)
• RST n (Register Indirect)
• PCHL (Register)
49
Branch Instructions
• Branching is used to control flow of prog execution
• Jump (Conditional or Unconditional
• Call and return (Conditional or unconditional)

and Programming
50
Examples
• Jump a 16bitaddress 2080H if carry

flag is set (Condition) • JC 2080H
• Uncondiotional Jump
• JMP 2080H
• Call a subroutine with its 16 buit
address
• CALL 3050H
• Return back from • RET
• Call a subroutine with its 16 bit
• CNC 3050H
address if carry flag is set
• Return if zero flag is set • RZ

and Programming
51
Stack, I/O and M/C Instructions

• PUSH rp (Register Indirect)
• PSUH PSW (Register Indirect)
• POP rp (Register Indirect)
• POP PSW (Register Indirect)
• XTHL (Register Indirect)
• SPPHL (Register)
• IN port (Direct)
• OUT port (Direct)
• EI (enable interrupt system)
• DI (Disable interrupt system)
• HLT (Halt operation)
• NOP (No operation)
• RIM
• SIM
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and Programming
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Programming 8085 MPU

• The programming model of any microprocessor is:
• Instruction set
• Register set
• Internal Architecture
• Memory Organization
• We will use assembly language to program 8085
processor
• An assembly language program consists of instruction
(usually one per line) each having at most 4 fields
• Label: Its optional and used to identify instruction line
• Op code: Always present. Represents the operation to be
performed
• Operand: Present most of the time. Represents values
• Comments: Optional. Gives additional information about the
instruction
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and Programming
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53
Programming 8085 MPU (Contd.)

• Consider the following example of an assembly
language instruction
MOV A, M ;Input data to accumulator
• ADD B ;Add accumulator with B
• MVI B, 01h ;Initialize the register B with 01h
• XRA A ;Clear Accumulator
• JMP LOOP ;Make a jump

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and Programming
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54

• Flowchart
• Graphical Representation of the program using special
shape symbols
• Source Program
• Listing of assembly language instructions
• Assembler
• A program that lets you write the program in assembly
language and then converts it into sequence of machine
codes

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and Programming
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55

• Program (Converting ASCII to BCD)
• Program:
 IN 01h ; Input ASCII data from port 01h

 ANI 0Fh ; AND with 0Fh to make BCD
 STA 2040h ; Store the result in
memory (2040h)
 HLT ; Stop

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and Programming
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56

• Program (Display Binary Count to port)
• Program code:
o XRA A ; Clear Accumulator

o LOOP: OUT 02h ; Output acc. To port 02h
o INR A ; Increment accumulator
o JMP LOOP ; Jump back to repeat

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and Programming
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57

• Program (Display Binary
Count to port) Modified
• Program counts and
displays so fast
• A delay routine provides
appropriate time interval
for a count to be seen and
observed

and Programming
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58
Program code:
 XRA A ; Clear Accumulator
 COUNT: OUT 02h ; Output acc. To port 02h
 INR A ; Increment accumulator
 MOV B, A ; Store count an B Register
 LXI H, FFFFh ; Initialize HL pair with a big number
 DELAY: DCX H ; Decrement HL by 1
 MOV A, L ; Move L to A
 ORA H ; Logically OR H and L to see if HL=0?
 JNZ DELAY ; If not zero then repeat with delay
 MOV A, B ; If yes then repeat next count
 JMP COUNT ;
59

• Program (Adding two 3-byte numbers)
• The accumulator can only handle 8-bit data
• In order to add 24-bit numbers, we first divide them into 8-
bit groups and then add them starting from LSB (recording
carry)
• The 8085 has special instruction “Add with Carry” to handle
such situation
• The procedure
• Add the LSB of both numbers and record the sum
• Add middle byte of 1st number, middle byte of 2nd numbers and
the carry generated in step 1. Store the partial sum
• Add the MSB of 1st number, MSB of 2nd number and the
previous carry and record the sum
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and Programming
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Program Code
LXI H 2020H ; Initialize HL register pair
MOV A, M ; Move LSB of first number into accumulator
INX H ; Increment pointer
ADD M ; Add LSBs of both numbers
STA 2026H ; Store the LSB of sum at memory location 2026h
INX H ; Increment memory pointer (2022h)
MOV A, M ; Move the middle byte of first number into accumulator
INX H ; Increment memory pointer
ADC M ; Add the middle bytes with carry
STA 2027H ; Store the sum of middle bytes at memory location 2027h
INX H ; Increment the memory pointer
MOV A, M ; Move the MSB of first number into accumulator
INX H ; Increment memory pointer
ADC M ; Add the MSB of both numbers with carry
STA 2028 ; Store the result of addition at memory location 202h
HLT2019
31 May ; Stop and Programming
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Questions
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MICROPROCESSOR SYSTEMS

PART 2- Microprocessor Architecture

PART 2- Microprocessor Architecture

PART 2- Microprocessor Architecture

• These are the set of 5 flip-flops −

PART 2- Microprocessor Architecture

PART 2- Microprocessor Architecture

PART 2- Microprocessor Architecture

PART 2- Microprocessor Architecture

PART 2- Microprocessor Architecture

PART 2- Microprocessor Architecture

PART 2- Microprocessor Architecture

PART 2- Microprocessor Architecture

• Operands, operation, result (where to

PART 2- Microprocessor Architecture

• Accumulated net result

PART 2- Microprocessor Architecture

It takes only takes one address to locate any item

Queue takes two addresses, last element, and first

PART 2- Microprocessor Architecture

Value of the TOS : ?

PART 2- Microprocessor Architecture

The Intel ® 8085 Pin Diagram and

8085 Pin Diagram (Fig.)

The Intel ® 8085 Pin Diagram and

The Intel ® 8085 Pin Diagram and

The Intel ® 8085 Pin Diagram and

Interrupts & Interrupt handler

PART 2- Microprocessor Architecture

PART 2- Microprocessor Architecture

• 8 or 16 bit data can be specified as a part of instruction.

MVI B 36H --------- 36H is copied into B register from memory

PART 2- Microprocessor Architecture

PART 2- Microprocessor Architecture

EG; CMA ----- complement data or content present

PART 2- Microprocessor Architecture

8085 Instruction Set

8085 Instruction Set (Contd.)

8085 Instruction Set (Contd.)

PART 2- Microprocessor Architecture

8085 Instruction Set (Contd.)

PART 2- Microprocessor Architecture

8085 Instruction Set (Contd.)

PART 2- Microprocessor Architecture

Data Transfer Instructions

PART 2- Microprocessor Architecture

Data Transfer Instructions

• MOV r1, r2 (Register)

• Move 8-bit no: 4F in reg B • MVI B, 4FH

• OUT 01H O/P ACC

PART 2- Microprocessor Architecture

• Add 8bit no 32H to ACC • ADI 32H

• Inc the content of reg D by 1

PART 2- Microprocessor Architecture

PART 2- Microprocessor Architecture

Logical and bit manipulation

• Logically AND reg H with ACC • ANA H

PART 2- Microprocessor Architecture

• Branching is used to control flow of prog execution

• Jump (Conditional or Unconditional

• Call and return (Conditional or unconditional)

PART 2- Microprocessor Architecture

• Jump a 16bitaddress 2080H if carry