CS322 – Computer Architecture

(CA)

Spring 2019
Section V3

Lecture 1: Introduction

Tanzeela Shakeel, University of Management and Technology, Lahore

Introduction
Instructor, Students and Course
 Instructor
 Tanzeela Shakeel
 Office: STD506 cabin 5
 Email: tanzeela.shakeel@umt.edu.pk

Monday Tuesday Wed. Thursday Friday

Counselling
Hours 9:30-1:00 11:00-2:00 11:00-2:00 09:30-1:00 11:00-2:00
Students
 Answer these questions (Not graded!)
1. Your name and city?
2. Your marks in FSC?
3. Why UMT?
4. Why IT?
5. Differentiate CS, SE and IT?
6. Your future plans?
7. Name any problem faced by Pakistan, can you suggest a
solution?
Course Description
 This course focus on the architecture of computer systems
hardware; instruction set architectures; MIPS; addressing
modes; register transfer notation; processor design and
computer arithmetic; memory systems; Cache; hardware
implementations of virtual memory, and input/output control
and devices.

 Course Page
 Moodle (http://lms.umt.edu.pk/)
 Search course ( Computer Architecture or Tanzeela
Shakeel)
 SST - School of Systems and Technology - undergraduate
courses
Textbook
 Textbook
 Patterson, David A. and John L. Hennessy. Computer Organization
and Design: The Hardware/Software Interface, Fifth edition
(softcopy available)
 Reference book
 Heuring, Vincent P. and Harry F. Jordan. Computer Systems Design
and Architecture, 2nd Edition. ISBN: 0-13-048440
 William Stallings, Computer Organization and Architecture: Designing for
Performance, Sixth Edition, Pearson Prentice Hall, Pearson Education,
Inc. Upper Saddle River, New Jersey, 2003

 Technology
 MARS IDE (MIPS)
 Xilinx
 Grading Policy
Instrument Description Weight
Class Exercises In-class exercises and evaluation 5%
Assignments Assigned during important stages of the course to apply and 10%
practice the learnt concepts

Quizzes In-class (un)announced 15 minutes tests 15%

Mid-Term Exam A single 75-minute exam from the material covered during 20%
the first 6-7 weeks

Final Exam Will cover the entire course. At least 75% of the material 40%
would be post mid term.

Term Paper/Project Will be assigned during the semester 10%

Late Submission Policy: Late submissions not allowed

 Tentative Course Outline
Week Contents Assessments

Digital Logic Design and Microprocessor and Assembly

1
Language review

Moore's Law, Performance Wall, Amdahl's Law,

2 Benchmark

Risc vs Cisc Architecture

3 MIPS Assembly Language

Operations of the Computer Hardware

4
Operands of the Computer Hardware
Signed and Unsigned Numbers
5 Representing Instructions in the
Computer
 Course Outline (cont.)
Week Contents Assessments
Logical Operations
Instructions for Making Decisions Assignment 3,
6
Quiz 3

7 MIPS 32 bit instruction set Address

Floating Point precision

8

9 Building Datapath Assignment 4

Quiz 4

10 Pipelining
 Course Outline (cont.)
Week Contents Assessments

11 Data hazard in Pipelining, Stalling Assignment 5

Control Hazard, Parallelism vs. Instruction

12 Quiz 5

13 Using predictions

Quiz 6
14 MemoryTechnology, Basic of Cache, cache Performance

15 Virtual machines,Virtual Memory,

Short Description
 Computer Architecture & Evolution/Revolution (History)
 Computer Performance
 Instruction Set Architecture/Design,
 Processor Implementation Techniques,
 Memory Hierarchy Design
 Design and implementation of a single cycle, multi cycle, and
pipelined processor with emphasis on the implementation of
control unit and performance of the main functional units,
i.e. ALU, Memory and registers.
Lets Start!
Computer Architecture
Computer
 An electronic device (or system of devices) which is used to
store, manipulate, and communicate information, perform
complex calculations, or control or regulate other devices or
machines, and is capable of receiving information . . . and of
processing it in accordance with variable procedural
instructions . . . used esp. for handling text, images, music,
and video, accessing and using the Internet, communicating
with other people (e.g. by means of email), and playing
games.
Classes of Computers
 Desktop computers
 General purpose, variety of software
 Subject to cost/performance tradeoff
 Server computers
 Network based
 Run large program for multiple user
 High capacity, performance, reliability
 Range from small servers to building sized
 Embedded computers
 Perform specific task
 Hidden as components of systems
 Stringent power/performance/cost constraints
Classes of computer
 Cloud Computer
 Contain Large collection of server that provides services over
the internet
 Supercomputer
 Preform High scientific and engineering problem at minimum
amount of time
 High cost and High performance
 Multi core processor
 Containing more than one processor in single Integrated Circuit
(IC)
What is the study of Computer
Architecture?
 It’s the study of the ___________ of computers
 Structure: static arrangement of the parts
 Organization: dynamic interaction of the parts and their
control
 Implementation: design of specific building blocks
 Performance: behavioral study of the system or of some of
its components
 Computer Design

Instruction Set Design Computer Hardware Design

 Machine Language
 Compiler View
 "Computer Architecture"
 "Instruction Set Processor“
 "Building Architect"
 Machine Implementation
 Logic Designer's View
 "Processor Architecture“
 "Computer Organization

Construction Engineer” Few people design computers! Very

few design instruction sets! Many people design computer
components. Very many people are concerned with computer
function, in detail
The Big Picture
 What is inside a computer?
 How does it execute my program?
The Big Picture
Architecture and Organization

 Architecture (the box outline, or interface)

 defines elements and interfaces between layers
 ISA: instructions, registers, addressing
 Organization (inside the box, or implementation)
 components and connections
 how instructions are implemented in hardware
 many different organizations can implement a
single architecture
 What is Computer Architecture?
Architecture is an interface between layers
 Provides functionality specification for software and
Programmer
 Provide design Specification for Hardware Designers
 ISA is the interface between hardware and software

 ISA is what is visible to the programmer (and ISA might be

different for O.S. and applications)
What is “Computer Architecture”?
Application
Operating
System
Compiler Firmware
Instruction Set
Architecture
Instr. Set Proc. I/O system
Datapath & Control
Digital Design
Circuit Design
Layout

 Coordination of many levels of abstraction

 Under a rapidly changing set of forces
 Design, Measurement, and Evaluation
 Layers of abstraction
 Abstraction
 Sophisticated Computer design: Create the
abstraction to hide the Complexity
 Think: an interface that exposes useable
behaviors
 isolates a layer from changes in the layer below
 improves developer productivity by reducing
detail needed to accomplish a task
 helps define a single architecture that can be
implemented with more than one organization
Computer Architecture
 Specification of how to program a specific
computer family
 what instructions are available?
 how are the instructions formatted into bits?
 how many registers and what is their function?
 how is memory addressed?
 how does I/O work?
 The MIPS architecture is the basis for the first
half of this course
Architecture Families
 IBM 360, 370, …
 PowerPC 601, 603, …
 DEC VAX, PDP-11
 Intel x86: 286, 386, 486, Pentium, P4,…
 Intel IA64 Itanium 1 & 2
 MIPS R2000, R3000, R4000, R5000, ...
 SUN Sparc
Computer Organization
The microarchitecture (organization)
How parts are assemble/tune/evaluate?
 the basic blocks of a computer system, more specifically
 basic blocks of the CPU
 basic blocks of the memory hierarchy
 how are the basic blocks designed, controlled,
connected?
 Organization used to be transparent to the ISA.
 Today more and more of the ISA is “exposed” to the
user/compiler.
 Computer Organization

 Processor
 datapath (functional units) manipulate the bits
 control hardware manages the manipulation
 Memory
 Registers – 100s of bytes, very fast, on the CPU
 cache memory – 1000s of bytes, fast, on the CPU
 main memory – millions of bytes, slower, off the CPU
 Input / Output
 interface to the rest of the world
A typical organization

main processor/memory bus

processor
memory

I/O bus

hard floppy CDROM serial network

disk disk drive ports interface
Computer Organization
What is Computer Architecture?
Easy Answer
Computer Architecture =
Instruction Set Architecture +
Machine Organization
Instruction Set Architecture
 Instruction set architecture (ISA)
 Contain all necessary information to write a
machine language program.
 Collection of all possible operations on a machine
 Includes:
 instruction set
 Number of bits to represent data
 machine memory
 programmer-accessible registers
Instruction Set Architecture
 A very important abstraction:
 interface between hardware and low-level software
 standardizes instructions, machine language bit patterns,
etc.
 advantage: allows different implementations of the same
architecture
 disadvantage: sometimes prevents adding new
innovations
 Modern instruction set architectures:
 80x86/Pentium/K6, PowerPC, DEC Alpha, MIPS, SPARC, HP
The Instruction Set: a Critical Interface

software

instruction set

hardware
Architecture and Organization

 Architecture is a layer of abstraction

 One architecture can be implemented with
many organizations
 One organization can support multiple
architectures
 Different manufacturing technologies
Forces on Computer Architecture
Technology Programming
Languages

Applications
Computer
Architecture

Operating
Systems
History
(A = F / M)
Below Your Program
 Application software
 Written in high-level language
 System software
 Compiler: translates HLL code to machine
code
 Operating System: service code
 Handling input/output
 Managing memory and storage
 Scheduling tasks & sharing resources

 Hardware
 Processor, memory, I/O controllers
 Levels of Program Code
 High-level language
 Level of abstraction closer to
problem domain
 Provides for productivity and
portability
 Assembly language
 Textual representation of
instructions
 Hardware representation
 Binary digits (bits)
 Encoded instructions and data
Levels of Representation
High Level Language temp = v[k];
Program v[k] = v[k+1];
v[k+1] = temp;
Compiler
lw $15, 0($2)
Assembly Language lw $16, 4($2)
Program sw $16, 0($2)
sw $15, 4($2)
Assembler
0000 1001 1100 0110 1010 1111 0101 1000
Machine Language 1010 1111 0101 1000 0000 1001 1100 0110
Program 1100 0110 1010 1111 0101 1000 0000 1001
0101 1000 0000 1001 1100 0110 1010 1111

Machine Interpretation

Control Signal ALUOP[0:3] <= InstReg[9:11] & MASK

Specification
°
°
 §1.3 Under the Covers
Components of a Computer
The BIG Picture  Same components for
all kinds of computer
 Desktop, server,
embedded
 Input/output includes
 User-interface devices
 Display, keyboard, mouse
 Storage devices
 Hard disk, CD/DVD, flash
 Network adapters
 For communicating with other
computers
Anatomy of a Computer

Output
device

Network
cable

Input Input
device device
 Inside the Processor
 AMD Barcelona: 4 processor cores
A Safe Place for Data
 Volatile main memory
 Loses instructions and data when power off
 Non-volatile secondary memory
 Magnetic disk
 Flash memory
 Optical disk (CDROM, DVD)
 The von Neumann Computer Architecture

 Stored-Program Concept – Storing programs as numbers

 Idea: A program is written as a sequence of instructions,
represented by binary numbers. The instructions are stored in the
memory just as data. They are read one by one, decoded and then
executed by the CPU.
 Same memory holds data, instructions.
 A single set of address/data buses between CPU and memory
Harvard Computer Architecture
 It is a computer architecture with physically separate storage
and signal pathways for program data and instructions
 Separate memories for data and instructions.
 Two sets of address/data buses between CPU and memory
 Harvard allows two simultaneous memory fetches.
RISC vs. CISC
 Reduced Instruction Set Computer (RISC)
 Compact, uniform instructions
 facilitate pipelining
 More lines of code
 large memory footprint
 Allow effective compiler optimization
 Complex Instruction Set Computer (CISC)
 Many addressing modes and long instructions
 High code density
 Often require manual optimization of assembly code for
embedded systems
Microprocessor
 Historical Perspective
 1944: The First Electronic Computer ENIAC at IAS,
Princeton Univ. (18,000 vacuum tubes)
 Decade of 70’s (Microprocessors)
Programmable Controllers, Single Chip Microprocessors
Personal Computers
 Decade of 80’s (RISC Architecture)
Instruction Pipelining, Fast Cache Memories
Compiler Optimizations
 Decade of 90’s (Instruction Level Parallelism)
Superscalar Processors, Instruction Level Parallelism (ILP),
Aggressive Code Scheduling, Out of Order Execution
 Decade of 2000’s (Multi-core processors)
Thread Level Parallelism (TLP), Low Cost Supercomputing
 Technology => Dramatic Change
 Processor
 2X in performance every 1.5 years; 1000X performance in last
decade (Moore’s Law)
 Main Memory
 DRAM capacity: 2x / 2 years; 1000X size in last decade
 Cost/bit: improves about 25% per year
 Disk
 capacity: > 2X in size every 1.5 years
 Cost/bit: improves about 60% per year
Technology Trends
 Electronics technology
continues to evolve
 Increased capacity and
performance
 Reduced cost
DRAM capacity

Year Technology Relative performance/cost

1951 Vacuum tube 1
1965 Transistor 35
1975 Integrated circuit (IC) 900
1995 Very large scale IC (VLSI) 2,400,000
2005 Ultra large scale IC 6,200,000,000
Moore’s law
 Number of IC resources will double every 18-24 months.
 Processor speed / number transistors doubling
approximately 18-24 months
 It includes:
 Feature Size shrink by 0.7x
 Number od transistor per die increases by 2x
 Speed of transitory increases by 1.2x
 Graph of Moore’s Law

51 EADS 11/01/2008
 Memory bottleneck
 The CPU can add two numbers in less than one nanosecond.
 If they are both in registers
 Putting a number from memory into a register takes about
100 nanoseconds.
 “Stall” – the CPU waits on memory.

52
Intel Haswell

Size/speed
1K / 1 ns

128Kb / 5 ns

1 Mb / 20 ns

4 Gb /125 ns

1 Tb / 1 ms

53
 GPU architecture
 GPUs have much less space devoted to cache.
 GPUs have multiple (100-1000) cores, which are simpler,
slower processing units.
 GPU cores all perform the same instructions, but on
different data.
 Not all the cores can be active at once. When one stalls,
another one starts up.

54
GPU and CPU: The Differences

ALU ALU
Control
ALU ALU

Cache

DRAM DRAM

CPU GPU

GPU
More transistors devoted to computation, instead of caching
or flow control
Suitable for data-intensive computation
High arithmetic/memory operation ratio
Intel Core i5-3470 Ivy Bridge Processor:
57