Flip Flops

Unit-4
Flip Flop

A basic sequential circuit is a flip-flop

Flip-flop has two stable states of complementary output values
SR Flip Flop
SR Flip Flop

SR (set-reset) flip-flop based on two nand gates

Clocked SR Flip Flop Circuit

Clock controlled flip-flop changes its state

only when the clock C is high
Clocked SR Flip Flop Circuit with Reset
Some flip-flops have asynchronous
preset Pr and clear Cl signals.
Output changes once these signals change, however
the input signals must wait for a change in clock
to change the output
Edge Triggered Flip Flop

Edge triggered flip-flop changes only

when the clock C changes
Positive Edge Triggered Flip Flop

Positive-edge triggered flip-flop changes only

on the rising edge of the clock C
Negative Edge Triggered JK Flip Flop
Other Flip Flops

T J D J
Q Q
f f f f
Q Q
K K

T Q D Q

f Q f Q

Toggle Flip-Flop Delay Flip-Flop (D-latch)

Race Problem

tloop
t

f
D Q t

1 f Q

Signal can race around during f = 1

Master-Slave Flip Flop Implementation
MASTER SLAVE

SI
J S Q S Q Q

RI
K R Q R Q Q

f
Master transmits the
PRESET signal
to the output during the
J Q high clock phase and
f
Q
slave is waiting for the
K
clock to change this
CLEAR prevents race conditions
Shift Registers
Shift Registers
RIPPLE Counter
UP- COUNTER
MOD-3 Counter
RING Counter
JHONSON Counter