Beruflich Dokumente
Kultur Dokumente
UNIT–I:
2
Microprocessor
3
Microprocessor Fifth Generation Pentium
Fourth Generation
During 1980s
Low power version of HMOS technology
(HCMOS)
Third Generation 32 bit processors
During 1978 Physical memory space 224 bytes = 16 Mb
HMOS technology Faster speed, Higher Virtual memory space 240 bytes = 1 Tb
packing density Floating point hardware
16 bit processors 40/ 48/ 64 pins Supports increased number of addressing
Easier to program modes
Dynamically relatable programs
Processor has multiply/ divide arithmetic Intel 80386
hardware
More powerful interrupt handling
capabilities Second Generation
Flexible I/O port addressing During 1973
NMOS technology Faster speed, Higher
Intel 8086 (16 bit processor) density, Compatible with TTL
4 / 8/ 16 bit processors 40 pins
First Generation Ability to address large memory spaces
Between 1971 – 1973 and I/O ports
PMOS technology, non compatible with TTL Greater number of levels of subroutine
4 bit processors 16 pins nesting
8 and 16 bit processors 40 pins Better interrupt handling capabilities
Due to limitations of pins, signals are 4
multiplexed Intel 8085 (8 bit processor)
Intel 4004
Intel 8008
Intel 8080
Intel 8085
1ntel 8086
1ntel 80286
Intel 80386
Intel 80486
Intel Pentium
Intel Pentium-ii
Intel Pentium-iii
Intel Pentium-iv
Intel Pentium -D
Intel Pentium core
Intel core 2
5
Intel 4004
Transistors: 2,300
6
Intel 8008:
Size: 10 micrometers
7
Zilog
Fairchild
Motorolla
8
9
10
Microprocessor Functional blocks
Introduction to 80286
12
8086 Microprocessor
Overview
13
Pins and signals
8086 Microprocessor
Pins and Signals Common signals
AD0-AD15 (Bidirectional)
Address/Data bus
15
8086 Microprocessor
Pins and Signals Common signals
MN/ MX
MINIMUM / MAXIMUM
TEST
READY
RESET (Input)
CLK
20
8086 Microprocessor
Pins and Signals Minimum mode signals
Pins 24 -31
DT/𝐑
ഥ (Data Transmit/ Receive) Output signal from the
processor to control the direction of data flow
through the data transceivers
Pins 24 -31
22
8086 Microprocessor
Pins and Signals Maximum mode signals
23
8086 Microprocessor
Pins and Signals Maximum mode signals
24
8086 Microprocessor
Pins and Signals Maximum mode signals
25
Architecture
27
8086 Microprocessor
Architecture
Segment
Registers
30
8086 Microprocessor
Architecture Bus Interface Unit (BIU)
31
8086 Microprocessor
Architecture Bus Interface Unit (BIU)
32
8086 Microprocessor
Architecture Bus Interface Unit (BIU)
33
8086 Microprocessor
Architecture Bus Interface Unit (BIU)
34
8086 Microprocessor
Architecture Bus Interface Unit (BIU)
35
8086 Microprocessor
Architecture Bus Interface Unit (BIU)
Instruction queue
A group of First-In-First-
Out (FIFO) in which up to
6 bytes of instruction
code are pre fetched
from the memory ahead
of time.
36
8086 Microprocessor
Architecture Execution Unit (EU)
EU decodes and
executes instructions.
A decoder in the EU
control system
translates instructions.
and
Some of the 16 bit registers can be
Index registers (Source used as two 8 bit registers as :
Index, Destination Index)
each of 16-bits AX can be used as AH and AL
BX can be used as BH and BL
CX can be used as CH and CL 37
DX can be used as DH and DL
8086 Microprocessor
Architecture Execution Unit (EU)
38
8086 Microprocessor
Architecture Execution Unit (EU)
39
8086 Microprocessor
Architecture Execution Unit (EU)
Example:
40
8086 Microprocessor
Architecture Execution Unit (EU)
41
8086 Microprocessor
Architecture Execution Unit (EU)
42
8086 Microprocessor
Architecture Execution Unit (EU)
43
8086 Microprocessor
Architecture Execution Unit (EU)
44
8086 Microprocessor
Architecture Execution Unit (EU)
Auxiliary Carry Flag
Carry Flag
Flag Register This is set, if there is a carry from the
This flag is set, when there is
lowest nibble, i.e, bit three during
addition, or borrow for the lowest a carry out of MSB in case of
nibble, i.e, bit three, during addition or a borrow in case
subtraction. of subtraction.
This flag is set, when the This flag is set, if the result of This flag is set to 1, if the lower
result of any computation the computation or comparison byte of the result contains even
is negative performed by an instruction is number of 1’s ; for odd number
zero of 1’s set to zero.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OF DF IF TF SF ZF AF PF CF
Tarp Flag
Over flow Flag If this flag is set, the processor
This flag is set, if an overflow occurs, i.e, if the result of a signed enters the single step execution
operation is large enough to accommodate in a destination
mode by generating internal
register. The result is of more than 7-bits in size in case of 8-bit
signed operation and more than 15-bits in size in case of 16-bit interrupts after the execution of
sign operations, then the overflow will be set. each instruction
Direction Flag Interrupt Flag
This is used by string manipulation instructions. If this flag bit
is ‘0’, the string is processed beginning from the lowest Causes the 8086 to recognize
address to the highest address, i.e., auto incrementing mode. external mask interrupts; clearing IF
Otherwise, the string is processed from the highest address disables these interrupts.
towards the lowest address, i.e., auto incrementing mode. 45
46
8086 Microprocessor
Architecture
8086 registers
categorized 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
into 4 groups OF DF IF TF SF ZF AF PF CF
Processor Memory
Registers inside a microcomputer
Store data and results temporarily
No speed disparity
Cost
Secondary Memory
Storage media comprising of slow
devices such as magnetic tapes and
disks
Hold large data files and programs:
Operating system, compilers,
databases, permanent programs etc. 50
8086 Microprocessor
Memory organization in 8086
8086 : 16-bit
Bank 0 : A0 = 0 Even
addressed memory bank
51
8086 Microprocessor
Memory organization in 8086
53
8086 Microprocessor
Interfacing SRAM and EPROM
54
8086 Microprocessor
Interfacing SRAM and EPROM
55
8086 Microprocessor
Interfacing SRAM and EPROM
56
8086 Microprocessor
Interfacing SRAM and EPROM
Monitor Programs
Programing 8279 for keyboard scanning and display
refreshing
Initialization of stack
57
8086 Microprocessor
Interfacing I/O and peripheral devices
I/O devices
For communication between microprocessor and
outside world
Ports / Buffer IC’s
Microprocessor I/ O devices
(interface circuitry)
Interrupt driven I/ O
I/O device interrupts the
processor and initiate data
transfer
Direct memory access
Data transfer is achieved by 58
bypassing the microprocessor
System bus cycle of 8086
59
8086 Microprocessor
8086 and 8088 comparison
The I/O ports or peripherals can be Only IN and OUT instructions can be
treated like memory locations and used for data transfer between I/O
so all instructions related to device and processor
memory can be used for data
transmission between I/O device
and processor
Data can be moved from any Data transfer takes place only
register to ports and vice versa between accumulator and ports
When memory mapping is used for Full memory space can be used for
I/O devices, full memory address addressing memory.
space cannot be used for
addressing memory. Suitable for systems which
require large memory capacity
Useful only for small systems
where memory requirement is less
For accessing the memory mapped For accessing the I/O mapped
devices, the processor executes devices, the processor executes I/O
memory read or write cycle. read or write cycle.
The 80286 CPU contains almost the same set of registers, as in 8086,
viz.
(a) Eight 16-bit general purpose registers
(b) Four 16-bit segment registers
(c) Status and control register
(d) Instruction Register
The flag register bits D0, D2, D4, D6, D7 and D11 are modified
according to the result of the execution of logical and arithmetic
instructions. These are called status flag bits.
Register Set of 80286
FLAG REGISTES
• The additional fields available in 80286 flag
registers are
• IOPL-I/O Privilege Field (bits D12 and D13)
• NT - Nested Task flag (bit D14)
• PE - Protection Enable (bit D16)
• MP – Monitor Processor Extension (bit D17)
• Processor Extension Evaluator (bit D19)
• Machine Status Flag (MSW) :
The machine status word consists of four flags.
These are – PE,MP,EM, and TS of the four lower
order bits D19 to D16 of the upper word of the
flag register. The LMSW and SMSW instructions
are available in the instruction set of 80286 to
write and read the MSW in real address mode
INTERNAL ARTECTURE OF
80286
80386 microprocessor
Features of 80386
Execution Unit:
Execution unit has 8 General and Special purpose
registers, which are either used for handling data or
calculating offset addresses.
The 64-bit barrel shifter increases the speed of all shift,
rotate.
Multiply/divide logic implements the bit-shift- rotate
algorithms to complete the operation in minimum time.
Instruction Unit:
Paging Unit:
It organizes physical memory in terms of pages of 4KB
size.
It works under the control of segmentation unit i.e.
each segment is divided into pages.
It converts linear addresses into physical addresses.
The control and attribute PLA checks privileges at
page level.
Bus Control Unit:
91
92
INTRODUCTION OF 80486
93
• 168PINS
• 32 ADDRESS PINS
• 32 DATA PINS
• Data Bus Width: 32 bit
• Address bus : 32 bit
• Memory Size: 4G +16K cache
94
NEED OF 80486 OVER 80386
95
PIN DIAGRAM
96
CLK2 ADDRESS
2X CLOCK A2 – A31
BUS
BE3#
32 BIT
DATA D – D DATA BE2#
0 31 32 – BIT
BUS ADDRESS
BE1# BYTE BUS
ADS#
ENABLINES
BE0#
BUS RDY#
CONTROL
W/R#
INTR
D / C#
NMI
PWT BRDY#
PAGE BLAST BUS CONTROL
CACHING #
CONTROL PCD
BS8#
BUS SIZE
BS16# CONTROL
FERR#
NUMERIC DP3
ERROR IGNNE DP2
REPORTING DP1
DP0 PARITY
ADDRESS BIT A20M#
20 MASK PCHK#
97
FEATURES OF 80486
98
• TIGHTELY COUPLED PIPELINING
– FETCHING,DECODING,ADDRESS TRANSULATION
OVERLAPED
– SINGLE CYCLE EXECUTION
99
100
REGISTERS
BP EBP
SP ESP
SEGMENT REGISTERS
CODE SEGMENT
CS
STACK SEGMENT
SS
DS
ES
DATA SEGMENT
FS
GS
IP EIP
FLAGS EFLAGS
101
Flag Register of 80486
FLAGS
31 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
E
F RESERVED FOR
L INTEL AC VM RF 0 NT IOPL OF DF IF TF SF ZF 0 AF 0 PF 1 CF
A
G
102
PENTIUM PROCESSOR
103
INTRODUCTION TO PENTIUM
104
Contd..
105
106
FEATURES OF PENTIUM
107
• Added second execution pipeline
– Superscalar performance
– Two instructions/clock
• Added branch prediction
108
109
PIN DIAGRAM
110
ARCHITECTURE
111
PENTIUM ARCHITECTURE
112
• Instruction Decode Unit:
• • It occurs in two stages – Decode1 (D1) and
Decode2(D2)
• • D1 checks whether instructions can be
paired
• • D2 calculates the address of memory
resident operands
• Prefetch Buffers:
• Four prefetch buffers within the processor works as
two
independent pairs. calculates the address of
memory resident operands
113
REGISTERS
114
115
116