Beruflich Dokumente
Kultur Dokumente
Suyampulingam.A
Dept of EEE.
ASE
Microprocessor Vs Processor
Computer is a large machine whereas
microprocessor is a small chip
Computer have their memory installed within it,
but microprocessors need external memory
Computer have graphical user interface whereas
microprocessors not
Computer can process a large amount of data
where as microprocessors can process a limited
amount of digital data mainly numeric values
Computer is an integrated system whereas
microprocessor is isolated chip.
Microprocessor
• The microprocessor is the CPU
• Essential component of the computer
• It is a silicon chip that comprises millions of transistors and other
electronic components
• Process millions of instructions per second.
• A Microprocessor is a versatile chip, that is combined with
memory and special purpose chips and pre-programmed by a
software
• It accepts digital data as i/p and processes it according to the
instructions stored in the memory.
• The microprocessor has many functions like functions of data
storage, interact with various other devices and other time
related functions.
• The main function is to send and receive the data to make the
function of the computer well.
Microprocessor Vs Processor
x y x y
C C
x C=1 y x C=1 y
x C=0 y x C=0 y
(a) (b)
• If C=1 y=x switch ON & x y x
buffer active C
floating x C = 0 y x
• If c=1, y is isolated
C & C
floating x C = 1 y x C = 1 y
• Bubble at input c
x C = 0 y x C = 0 y
signifies inversion
(a) (b)
• illustration of use of tri state
TS1
L
L
C C
N N
M
M
TS2
(a) (b)
A B
C2
C1 Segment 2
Segment 1
C4
C3
D E
Bus
Register
8
R1
bus
R2
Register
Register file
• Serial register file
• Parallel Register file
b0 b1 b2 b7
Register with address A3
Register Files
A3 Byte 1 Byte 2
Output Byte 1
FIFO ~ LIFO comparison
FIFO LIFO
LIFO – STACK
Important component of a Micro Controller
Data in to top of stack
Parallel register file(memory)
• A parallel register file
• Locations accessed in parallel
• for read/write
• Various types
Basic memory cell(Built around RSFF)
WR
TS1
Din
D
TS2
Dout
RD
CLK
Addressing - File register
• To select a particular register within a file register, addressing
is used.
Illustrates formation of memory/
register file using memory cells
4 decoded address lines
b0 b1 b7
2-to-4 address decoder
L0
2-bit address
A0 b0 b1 b7
L1
A1
L2 b0 b1 b7
L3
b0 b1 b7
d0 d1 d7
WR RD
CLR WR RD
CS
Memory address
Memory
register
of 2n X 8
Address size
bus
Decoded 8
address
lines Data bus
Block diagram- memory block
CS RD WR CLR
Address Bus
( n bits ) Memory
Address Memory
Register (2^n X 8)
(MAR)
Data bus
CS- chip select, only if CS=1, then address selection is done ( 8 bits)
Contd…
• CS – Chip selected
• Common select input to whole unit
• Any location selection for RD/WR
• done only if CS=1
• CS used to increase memory capacity
READ timing diagram
Address lines
CS
RD
Data lines
tp1 tp2
Write timing Diagram
Address lines
CS
WR
Data lines
CLK
t1 t2 t3
Types of memory
1. Random access memory (RAM)
RE O/P
RAM File Register Reg
WE 8 bit X 128
RCLK
OCLK
RAM Address
Decoder
IE
RAMACLK
RAWE RAM Address
Register
I/P
7 bit address
Reg
WR
WW W-Reg
WCLK ICLK
An elementary processor
OWE OE
Output register
RE
RCLK Output
WE
Data bus
RAM address OCLK
decoder
IE
RAM address
register RAMACLK
Input register
Memory
RAWE address Input
WR
Working register
WCLK
ICLK
WW
Operations
• Memory read
– 7 bit address provided
– RAWE enabled
– RAMACLK transition, address latched
– RE enabled
– Output port of RAM connected to data bus
– Data available on data bus
Contd…
• Memory write
– 7 bit address provided
– RAWE enabled
– RAMACLK- address latched
– WE- enabled
– Input port connected to data bus
– RCLK transition - data in data bus is written to
RAM ( to the address specified)
Contd…
• Input port
– ICLK transition- data from outside is latched to
input register.
– IE- enabled, connected to data bus.
• Output port
– OWE enabled, data bus connected to output
register.
– OCLK transition, data latched to o/p reg.
– OE enabled, data available on output port.
Contd…
• Working register.
– WW enabled, data bus connected to W-reg
– WCLK transition, data latched to Wreg.
– WR enabled, data read from W-reg to data bus.
Generation of clocks
Status of control lines
3 0 0 1 0 0 0 1 Wreg to RAM
4 0 0 0 0 1 0 1 Wreg to output
WE 8 bit X 128
Instruction RCLK
Register
CLK
OCLK
Instruction RAM Address
Decoder Decoder
IE
RAMACLK
RAWE RAM Address
Control Register
Signals I/P
7 bit address
Reg
WR
WW W-Reg
WCLK ICLK
Program
Counter
Program
Memory
O/P
RAM File Register Reg
Instruction
RAM Address Decoder
Register
Instru
N N+ 1 N+ 2 N+ 3
cyc
Write Write
Processed data Processed data
Fetch instruction at location P Fetch instruction at location P+1 Fetch instruction at location P+2 Fetch instruction at location P+3
Execute instruction at location P-1 Execute instruction at location P Execute instruction at location P+1 Execute instruction at location P+2
Machine cycle N