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15EEE314

Microcontrollers and Applications

Suyampulingam.A
Dept of EEE.
ASE
Microprocessor Vs Processor
Computer is a large machine whereas
microprocessor is a small chip
Computer have their memory installed within it,
but microprocessors need external memory
Computer have graphical user interface whereas
microprocessors not
Computer can process a large amount of data
where as microprocessors can process a limited
amount of digital data mainly numeric values
Computer is an integrated system whereas
microprocessor is isolated chip.
Microprocessor
• The microprocessor is the CPU
• Essential component of the computer
• It is a silicon chip that comprises millions of transistors and other
electronic components
• Process millions of instructions per second.
• A Microprocessor is a versatile chip, that is combined with
memory and special purpose chips and pre-programmed by a
software
• It accepts digital data as i/p and processes it according to the
instructions stored in the memory.
• The microprocessor has many functions like functions of data
storage, interact with various other devices and other time
related functions.
• The main function is to send and receive the data to make the
function of the computer well.
Microprocessor Vs Processor

• Microprocessors are small chips that can be


used to perform some specific functions like
processing digital data.
• Computers are made up of a wide range of
components combined together which
consists of microprocessors, processors(CPU),
memory, buses, capacitors, inductors, etc to
make a powerful computational machine
Evolution of Microprocessors
General-purpose microprocessor
• CPU for Computers
• Commonly no RAM, ROM, I/O on CPU chip
itself
Data Bus
CPU
General-
Serial
Purpose RAM ROM I/O Timer COM
Micro- Port
Port
processor
Address Bus
Components of a
microprocessor/controller
• CPU: Central Processing Unit
• I/O: Input /Output
• Bus: Address bus & Data bus
• Memory: RAM & ROM
• Timer
• Interrupt
• Serial Port
• Parallel Port
Microcontroller
• A single-chip computer
• On-chip RAM, ROM, I/O ports...
• Example:Motorola’s 6811, Intel’s 8051,
Zilog’s Z8 and PIC 16X
Microprocessor vs. Microcontroller
Microcontroller
Microprocessor
• CPU, RAM, ROM, I/O and timer
• CPU is stand-alone, RAM, ROM, I/O,
are all on a single chip
timer are separate
• fixed amount of on-chip ROM,
• designer can decide on the amount of
RAM, I/O ports
ROM, RAM and I/O ports.
• for applications in which cost,
• expensive
power and space are critical
• versatility
• single-purpose (control-oriented)
• general-purpose
• Low processing power
• High processing power
• Low power consumption
• High power consumption
• Bit-level operations
• Instruction sets focus on processing-
• Instruction sets focus on control
intensive operations
and bit-level operations
• Typically 32/64 – bit
• Typically 8/16 bit
• Typically deep pipeline (5-20 stages)
• Typically single-cycle/two-stage
pipeline
Microcontrollers Manufacturing
Companies
• Intel 8051
• Microchip Technology PIC
• Atmel AVR
• Texas Instruments MSP430 (16-bit)
• Motorola MC68HC05,
• National COP800,
• SGS/Thomson ST62,
• Zilog Z86Cxx
• Silicon Labs
• Renesas Technology Corp
• Dallas Semiconductor
• Fujitsu Semi conductor Europe
• ST Microelectronics
• ZiLog Company
• Freescale Semiconductor Company
MEMORY
Definitions
• Bus - A group of data lines, through which
data traverse.
• Bus Width - number of individual data lines in
a bus. (no. of bits that can flow at a time).
• Register- memory units arranged in a
sequence. Eg. 4 bit register, 8 bit register etc.
• File register- A group of registers.
Tristate buffer
• Electronic amplifier
• An amplifier to provide drive capacity
• If input is at 0, output too is at 0
• If input is at 1, output is at 1
• A buffer can be provided with a Gate control input C
Tristate buffer

x y x y

C C

x C=1 y x C=1 y

x C=0 y x C=0 y

(a) (b)
• If C=1 y=x switch ON & x y x

buffer active C

• If c=0, y is isolated & x C = 1 y x

floating x C = 0 y x

• y is at ‘tri-state’ (a) (b)

• If c=0, y=x, switch ON


y y
& bufferxactive x

• If c=1, y is isolated
C & C

floating x C = 1 y x C = 1 y
• Bubble at input c
x C = 0 y x C = 0 y
signifies inversion
(a) (b)
• illustration of use of tri state
TS1
L
L

C C
N N
M
M
TS2
(a) (b)

• buffer for 2-1 mux


• If C=1, N=L
• C=0, N=M
• Provision of separate controls for TS1 & TS2
•  N can be connected elsewhere
• TS buffer brings flexibility to connections
Digital Circuit configuration-tri state
buffers

A B
C2
C1 Segment 2

Segment 1
C4
C3

D E
Bus
Register

8
R1
bus

R2

Register
Register file
• Serial register file
• Parallel Register file

Register with address A0 b0 b1 b2 b7

Register with address A1 b0 b1 b2 b7

Register with address A2 b0 b1 b2 b7

b0 b1 b2 b7
Register with address A3
Register Files

A set of registers arranged in an orderly manner


 Register File
Data serially shifted
Serial  data loaded/rea d one after another IN at top
serially/sequentiall y
Data serially shifted
Access is in serial form – one behind another
OUT at bottom
8 SRS arranged side by side
In same order
Designated b0 , b1,.b6 , b7
Byte- wide
First-IN-First-Out
FIFO
Each SR has 4 stages
Stages assigned addresses A 0 , A1, A 2 , & A3
Regist Status Status Status Status Status Status
er before 1st after 1st after 2nd after 3rd after 4th after 5th
addre clock pulse clock clock pulse clock pulse clock pulse clock pulse
ss pulse↓ ↓ ↓ ↓ ↓

A0 Byte 1 Byte2 Byte 3 Byte 4 Byte 5

A1 Byte 1 Byte 2 Byte 3 Byte 4

A2 Byte 1 Byte 2 Byte 3

A3 Byte 1 Byte 2

Output  Byte 1
FIFO ~ LIFO comparison

FIFO LIFO

Register file – modify to move data


up or down

LIFO – STACK
Important component of a Micro Controller
Data in  to top of stack
Parallel register file(memory)
• A parallel register file
• Locations accessed in parallel
• for read/write
• Various types
Basic memory cell(Built around RSFF)
WR

TS1
Din
D
TS2
Dout
RD
CLK
Addressing - File register
• To select a particular register within a file register, addressing
is used.
Illustrates formation of memory/
register file using memory cells
4 decoded address lines

b0 b1 b7
2-to-4 address decoder

L0
2-bit address

A0 b0 b1 b7
L1
A1
L2 b0 b1 b7

L3
b0 b1 b7

d0 d1 d7
WR RD

Byte-wide data lines


File has 8  4  32 cells.
D lines of all 4b0 connected  d o
similarly with d1, d 2 ...d 6 , d 7
8 data lines - byte wide
4 addresses - L0 , L1, L2 , & L3
WR & RD lines

2 address lines - A 0 & A1


decoded into addresses L 0  L3
by 2 - 4 address decoder
A memory unit - -
n address lines  2n locations.
8 data lines  byte- wide
CLK, WR & RD common
Any location accessed with equal ease.

RANDOM ACCESS MEMORY


‘RAM’ memory

RAM used to store / retrieve data at short notice


‘Scratch Pad Memory’
RAM/Scratch pad
Capacity in Micro Controller
~ 32 to 65k
Normally power of 2
Typical RAM

CLR WR RD
CS

Memory address
Memory

register
of 2n X 8
Address size
bus

Decoded 8
address
lines Data bus
Block diagram- memory block
CS RD WR CLR

Address Bus
( n bits ) Memory
Address Memory
Register (2^n X 8)
(MAR)

Data bus
CS- chip select, only if CS=1, then address selection is done ( 8 bits)
Contd…
• CS – Chip selected
• Common select input to whole unit
• Any location selection for RD/WR
• done only if CS=1
• CS used to increase memory capacity
READ timing diagram

Address lines

CS

RD

Data lines

tp1 tp2
Write timing Diagram
Address lines

CS

WR

Data lines

CLK

t1 t2 t3
Types of memory
1. Random access memory (RAM)

– Static RAM (SRAM)


• Flip flop based logic.
• Once a ‘bit’ is written, it stays until it is changed in a subsequent write
operation.
– Dynamic RAM (DRAM)
• MOS transistor is used.
• Gate of MOS accumulates charge and decides on/off.
• In time (ms) charge depletes.
• Requires replenishing of charge at regular intervals.
• Less size, high price.

Volatile Memory – doesn’t retain data if power goes. (RAM)


• Non - Volatile Memory- Data retained even when power goes
OFF(ROM)
Contd…
2. Read Only memory (ROM) – non volatile
Cannot be erased, manufacturer writes data.
• Data written during manufacture
• It can be read repeatedly
• No writing
• No erasure
• ROM manufacturer wants data to be given in a specified
format/template.
• Examples: Programs in calculator and cell phones
3.PROM- Programmable ROM
– Can be programmed only once.
4.EPROM- Erasable PROM
– Exposure to UV light can erase PROM.
5.EEPROM- electrically erasable, selective erase also.
Bulk storage devices ( non Volatile)
• Magnetic storage- floppy disk, Hard disk
drives.
• Optical storage- CD
– Blue laser - DVD, Blueray etc
• Flash memory- USB,
• Flash E2PROM
• More recent
• Compact/Portable
• Directly plugged into PC USB port
• Capacity more than 1GB
Data Transfer Unit (DTU)

• Set of functional elements linked together to


perform data transfer.
– Functional elements
• Memory (RAM)
• Address decoder
• Address register
• Input and output
• Working register
8
OWE OE
in out

RE O/P
RAM File Register Reg

WE 8 bit X 128
RCLK

OCLK
RAM Address
Decoder

IE
RAMACLK
RAWE RAM Address
Register
I/P
7 bit address
Reg
WR
WW W-Reg
WCLK ICLK
An elementary processor
OWE OE

Output register
RE

RAM file registers

RCLK Output

WE

Data bus
RAM address OCLK
decoder

IE

RAM address
register RAMACLK

Input register
Memory
RAWE address Input

WR

Working register
WCLK
ICLK

WW
Operations

• Memory read
– 7 bit address provided
– RAWE enabled
– RAMACLK transition, address latched
– RE enabled
– Output port of RAM connected to data bus
– Data available on data bus
Contd…
• Memory write
– 7 bit address provided
– RAWE enabled
– RAMACLK- address latched
– WE- enabled
– Input port connected to data bus
– RCLK transition - data in data bus is written to
RAM ( to the address specified)
Contd…
• Input port
– ICLK transition- data from outside is latched to
input register.
– IE- enabled, connected to data bus.
• Output port
– OWE enabled, data bus connected to output
register.
– OCLK transition, data latched to o/p reg.
– OE enabled, data available on output port.
Contd…
• Working register.
– WW enabled, data bus connected to W-reg
– WCLK transition, data latched to Wreg.
– WR enabled, data read from W-reg to data bus.
Generation of clocks
Status of control lines

S. RAWE RE WE IE OWE W WR Activity


No. W

01 0 0 0 1 0 1 0 Transfer data from input port to


working register

02 1 0 0 0 0 0 0 Write address into RAM address


register (get ready to select an address
location in the register file)

03 0 0 1 0 0 0 1 Transfer data from working register


into the selected RAM location

04 0 0 0 0 1 0 1 Transfer data from working register to


the output port

05 0 1 0 0 0 1 0 Transfer data from selected RAM


location into the working register

06 0 1 0 0 1 0 0 Transfer data from selected RAM


location into the output port

07 0 0 1 1 0 0 0 Transfer data from input port to the


input register
DTU Operations

S.no RAWE RE WE IE OWE WW WR

1 0 0 0 1 0 1 0 Input port to Wreg

2 1 0 0 0 0 0 0 Address latched to RAM address reg

3 0 0 1 0 0 0 1 Wreg to RAM

4 0 0 0 0 1 0 1 Wreg to output

5 0 1 0 0 0 1 0 RAM to work Reg

6 0 1 0 0 1 0 0 RAM to output port

7 0 0 1 1 0 0 0 Input port to RAM

Operational Code- OPCODE


Enhanced Data Transfer Unit (EDTU)

• Set of functional elements linked together to


perform data transfer.
– Functional elements
• Memory (RAM)
• Address decoder
• Address register
• Input and output
• Working register
• Program Counter
• Program Memory
• Instruction Register
8
Program OWE OE
Counter in
Program out
Memory
CLK
RE O/P
CLK
RAM File Register Reg

WE 8 bit X 128
Instruction RCLK
Register
CLK
OCLK
Instruction RAM Address
Decoder Decoder

IE
RAMACLK
RAWE RAM Address
Control Register
Signals I/P
7 bit address
Reg
WR
WW W-Reg
WCLK ICLK
Program
Counter
Program
Memory
O/P
RAM File Register Reg

Instruction
RAM Address Decoder
Register

RAM Address Register


Instruction
Decoder
One byte data from can
be subjected to
- Complement
- Increment
- Decrement I/P
W-Reg Reg
One byte data from RAM
Another from WR s.t
- AND
- OR
- XOR
Instruction
Many operations involve working register
Each op. requires clock input
Operations done in sequence for complex transfers
Each operation called -- ‘INSTRUCTION’
Example : transfer data from RAM location Ls to RAM location Ld
Write address of Ls into RAM address register –
Execute Instruction No.2
Transfer data from Ls into working register –
Execute instruction No.3
Write address of Ld into RAM address register –
Execute instruction No. 2
Transfer data from working register to Ld –
Execute instruction No.3
Enhanced DTU
• One application wants one instruction sequence
• to be carried out or executed
• another has another instruction sequence to
be executed
• Each application  characteristic instruction
sequence
• To be executed
• Instruction sequence to be executed 
‘PROGRAM
Program Memory
• PROGRAM to be executed stored in a separate
memory called ‘Program Memory’
• Each instruction in program memory is to be
• fetched and loaded into a register
» ’Instruction Register’

• Content of instruction register directly


• connected to relevant DTU control line
Program Counter
• Program counter – PC
• Keeps track of the serial number of instruction
executed
• PC specifies next location in program memory
– Fetch next instruction from there
– Execute
– Increment PC content
Add
PC
IR
PM to DTU
Enhanced DTU
• Instruction – a binary word
• operation code
• ‘OPCODE’
• Mnemonic
• Collection of instructions – Instruction set

Each instruction sequence executed  program


Example : meaningful programs
Read a number of bytes from an input port
& store in successive RAM locations
Take a set of bytes from successive RAM locations
&output at a port
Add bytes in successive RAM locations & output sum
Take a byte in one location and XOR it with bytes in 8
successive locations in RAM
• IDE-Integrated Development
Environment.(source code Editor, Compiler,
Interpreter, build automation tools and a
debugger)(s/w and H/w)
• Compiler(program) -High Level language
Machine/binary language
• Assembler(program) -low (assembly)Level
language Machine/binary language
Instruction cycle
• Fetch cycle + Execute cycle Machine cycle/
Instruction cycle
• Program Execution  carry out successive
machine
Timing Diagram
1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 1

Instru
N N+ 1 N+ 2 N+ 3
cyc

Increment PC to P Increment PC to P+1 Increment PC to P+2 Increment PC to P+3

Fetch instruction at Fetch instruction at Fetch instruction at


location P & load into IR location P+1 & load into IR location P+2 & load into IR

Decode instruction Fetched Decode instruction Fetched Decode instruction Fetched


in instruction cycle N in instruction cycle N+1 in instruction cycle N+2

Fetch data Fetch data Fetch data

Process data Process data Process data

Write Write
Processed data Processed data

Fetch instruction at location P Fetch instruction at location P+1 Fetch instruction at location P+2 Fetch instruction at location P+3

Execute instruction at location P-1 Execute instruction at location P Execute instruction at location P+1 Execute instruction at location P+2

Machine cycle N

Machine cycle N+1

Machine cycle N+2

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