PCIe

Peripheral Component Interconnect - Express

Features
• little endian
• point-to-point topology
• 4KB of config registers
• burst oriented (deals data in transactions)
• scalable (lane aggregation)
PCIe stack
• Transaction layer
• Data link layer
• Physical layer
PCIe Bus
• Bus Enumeration
• vendor ID and device ID
• Bus <- Dev <- Function
• Bus Master
• Bus Contention
• Bus Arbitration
Config Space
• uses a fixed addressing scheme
• can request up to six areas of memory
space or I/O port space via its
configuration space registers
• access through CF8h and CFCh 32-bit IO
location
Base Address Registers
• point to the location in the system address space
• can be IO space or Memory space mapped
• each bar is 32-bit
• Concat two BARS for 64-bit addressing
• Bit 0 - Mem or IO
• Mem: BAR[x] & FFFFFFF0h
• IO: BAR[x] & FFFFFFFCh
• Get BAR address size
• Send FFFFFFFF to the BAR[x]
• 0's returned in don't care bits
• ~(BAR[x]) is the size
Interrupts
• four interrupt lines
• are not wired in parallel
• interrupt lines are level-triggered
• message-signaled interrupts
• performs a memory write, instead of asserting a dedicated line.
• alleviates the problem of scarcity of interrupt lines.
• PCIe does not have physical interrupt lines and uses MSI exclusively
• has same latency as mem R/W
PCIe driver
• Enable the device
• Request MMIO/IOP resources
• Set the DMA mask size
• Access device configuration space (if needed)
• Register IRQ handler
• Enable DMA/processing engines