Beruflich Dokumente
Kultur Dokumente
Anselmo Lastra
Some capacity 2k
k bits of address lines
Often multiplexed
Maybe have read line, clock, chip
select
Have a write enable line
defparam R1.INIT_00 =
64'h08192A3B4C5D6E7F08192A3B4C5D6E7F08192A3B4
C5D6E7F08192A3B4C5D6E7F; // 256-bit hex value
defparam R1.INIT_01 =
64'h08192A3B4C5D6E7F08192A3B4C5D6E7F08192A3B4
C5D6E7F08192A3B4C5D6E7F; // 256-bit hex value
...
defparam R1.INIT_0F =
64'h08192A3B4C5D6E7F08192A3B4C5D6E7F08192A3B4
C5D6E7F08192A3B4C5D6E7F; // up to INIT_0F
//synopsys translate_on
http://www.cs.unc.edu/~lastra/comp190/Assignments/block_ram_C.txt
Delay until
data
available
1,2,4,8 or
full page
Burst or single 2 or 3 Order or
0 accesses
The UNIVERSITY of NORTH CAROLINA at CHAPEL HILL
DRAM Links
DRAM on XSA-100 board
http://www.hynix.co.kr/datasheet/pdf/dram/(2)HY57V281620A(L)T-I.PDF
Datasheets
http://www.hynix.co.kr/datasheet/pdf/dram/(2)HY57V281620A(L)T-I.PDF
http://download.micron.com/pdf/datasheets/dram/128msdram_f.pdf
http://www.infineon.com/cmc_upload/documents/018/329/hb39s128CT.pdf
Verilog model
http://download.micron.com/downloads/models/verilog/sdram/sdr/128meg/
mt48lc8m16a2.zip