Introduction to Computing

Systems and Programming

Digital Logic Structures

 Logical Operations

 0, 1 in a binary value can represent logical

TRUE = 1, or FALSE = 0.
 We can perform logical operations on binary
bits or a set of binary bits, also known as
Boolean algebra.
 The basic operations are AND, OR, NOT

Introduction to Computing Systems and Programming Fall 1384, 2

 Basic Logic Operations
Truth Tables of Basic Operations
AND OR
NOT A B A.B A B A+B
A A' 0 0 0 0 0 0
0 1 0 1 0 0 1 1
1 0 1 0 0 1 0 1
Equivalent Notations
1 1 1 1 1 1
 Not A = A’ = A
 A and B = A.B = A∧B = A intersection B
 A or B = A+B = A∨B = A union B
Introduction to Computing Systems and Programming Fall 1384, 3
 More Logic Operations

 XOR and XNOR

XOR XNOR
A B A⊕B A B (A⊕B)’
0 0 0 0 0 1
0 1 1 0 1 0
1 0 1 1 0 0
1 1 0 1 1 1

Introduction to Computing Systems and Programming Fall 1384, 4

 Logical Operations Example
 AND
11000101
 useful for clearing bits
AND 00001111
 AND with zero = 0
 AND with one = no change 00000101
 OR
 useful for setting bits
11000101
 OR with zero = no change OR 00001111
 OR with one = 1 11001111
 NOT
 unary operation -- one argument NOT 11000101
 flips every bit 00111010
Introduction to Computing Systems and Programming Fall 1384, 5
 Simple Switch Circuit
 Switch open:
– No current through circuit
– Light is off
– Vout is +2.9V
 Switch closed:
–
Short circuit across switch
–
Current flows
Light is on –
– Vout istwo
Switch-based circuits can easily represent
0V
states:
on/off, open/closed, voltage/no voltage.
Introduction to Computing Systems and Programming Fall 1384, 6
 Transistor

 Microprocessors contain millions of

transistors
 Intel Pentium II: 7 million
 Intel Pentium III: 28 million
 Intel Pentium 4: 54 million

 Logically, each transistor acts as a switch

Introduction to Computing Systems and Programming Fall 1384, 7

 N-type MOS Transistor
 MOS = Metal Oxide Semiconductor
– two types: N-type and P-type
 N-type
– when Gate has positive voltage,
short circuit between #1 and #2
(switch closed)
– when Gate has zero voltage, Gate = 1
open circuit between #1 and #2
(switch open)

Terminal #2 must be Gate = 0

connected to GND (0V).

Introduction to Computing Systems and Programming Fall 1384, 8

 P-type MOS Transistor
 P-type is complementary to N-type
 when Gate has positive voltage,
open circuit between #1 and #2
(switch open)
 when Gate has zero voltage,
short circuit between #1 and #2 Gate = 1
(switch closed)

Terminal #1 must be Gate = 0

connected to +2.9V.

Introduction to Computing Systems and Programming Fall 1384, 9

 CMOS Circuit
 Complementary MOS
 Uses both N-type and P-type MOS transistors
 P-type
 Attached to + voltage
 Pulls output voltage UP when input is zero

 N-type
 Attached to GND
 Pulls output voltage DOWN when input is one

 For all inputs, make sure that output is either

connected to GND or to +, but not both!
Introduction to Computing Systems and Programming Fall 1384, 10
 Inverter (NOT Gate)

Truth table

In Out In Out
0 V 2.9 V 0 1
2.9 V 0V 1 0

Introduction to Computing Systems and Programming Fall 1384, 11

 NOR Gate
2.9 v

A P

B P
C

A B C
N 0 0 1
0 1 0
N
1 0 0
0v 1 1 0
0v
Introduction to Computing Systems and Programming Fall 1384, 12
 NOR Gate Operation
2.9 v 2.9 v 2.9 v

2.9 v 2.9 v
0v P P
P

2.9 v 0v
0v P P P
2.9 v 0v 0v

N N N

N N
N
0v 0v 0v
0 v Systems and Programming
Introduction to Computing 0v 0 v 13
Fall 1384,
 OR Gate

A B C
0 0 0
0 1 1
1 0 1
1 1 1

Add inverter to NOR.

Introduction to Computing Systems and Programming Fall 1384, 14

 NAND Gate (AND-NOT)

A B C
0 0 1
0 1 1
1 0 1
1 1 0
Introduction to Computing Systems and Programming Fall 1384, 15
 AND Gate
A B C
0 0 0
0 1 0
1 0 0
1 1 1

Add inverter to NAND.

Introduction to Computing Systems and Programming Fall 1384, 16

 Basic Logic Gates

Introduction to Computing Systems and Programming Fall 1384, 17

 More Inputs
 AND/OR can take any number of inputs.
 AND = 1 if all inputs are 1.
 OR = 1 if any input is 1.
 Similar for NAND/NOR.

 Can implement with multiple two-input gates,

or with single CMOS circuit.

Introduction to Computing Systems and Programming Fall 1384, 18

 Logical Completeness
 Can implement ANY truth table with AND, OR, NOT.
A B C D
1. AND combinations
0 0 0 0
that yield a "1" in the
0 0 1 0 truth table.
0 1 0 1
0 1 1 0
1 0 0 0 2. OR the results
of the AND gates.
1 0 1 1
1 1 0 0
1 1 1 0
Introduction to Computing Systems and Programming Fall 1384, 19
 Practice

 Implement the following truth table.

A B C A B C
0 0 0 0 0 1
0 1 1 0 1 0
1 0 1 1 0 0
1 1 0 1 1 1

Introduction to Computing Systems and Programming Fall 1384, 20

 Summary
 MOS transistors are used as switches to implement
logic functions.
 N-type: connect to GND, turn on (with 1) to pull down to 0
 P-type: connect to +2.9V, turn on (with 0) to pull up to 1

 Basic gates: NOT, NOR, NAND

 Logic functions are usually expressed with AND, OR, and NOT

 Properties of logic gates

 Completeness
 can implement any truth table with AND, OR, NOT
 DeMorgan's Law
 convert AND to OR by inverting inputs and output
Introduction to Computing Systems and Programming Fall 1384, 21
 Logic Structures
 We've already seen how to implement truth tables
using AND, OR, and NOT -- an example of
combinational logic.

 Combinational Logic Circuit

 output depends only on the current inputs
 stateless
 Sequential Logic Circuit
 output depends on the sequence of inputs (past and
present)
 stores information (state) from past inputs
Introduction to Computing Systems and Programming Fall 1384, 22
 Decoder
 n inputs, 2n outputs
 exactly one output is A i=0
1 for each possible B 1, iff A,B is 00
input pattern
i=1
1, iff A,B is 01

i=2
1, iff A,B is 10

i=3
1, iff A,B is 11

Introduction to Computing Systems and Programming Fall 1384, 23

 Multiplexer
 n-bit selector and 2n inputs, one output
 output equals one of the inputs, depending on
selector

4-to-1 MUX
Introduction to Computing Systems and Programming Fall 1384, 24
 Half Adder

 Half Adder A B C S
 2 inputs 0 0 0 0
0 1 0 1
 2 outputs: sum and carry 1 0 0 1
1 1 1 0

Introduction to Computing Systems and Programming Fall 1384, 25

 Full Adder
 Add two bits and carry-in,
produce one-bit sum and carry-out.
A B Cin S Cout
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
Introduction to Computing Systems and Programming Fall 1384, 26
 Four-bit Adder

Introduction to Computing Systems and Programming Fall 1384, 27

 Combinational vs. Sequential
 Combinational Circuit
 always gives the same output for a given set of inputs
 ex: adder always generates sum and carry,
regardless of previous inputs
 Sequential Circuit
 stores information
 output depends on stored information (state) plus input
 so a given input might produce different outputs,
depending on the stored information
 example: ticket counter
 advances when you push the button
 output depends on previous state

 useful for building “memory” elements and “state machines”

Introduction to Computing Systems and Programming Fall 1384, 28
 R-S Latch
1 1
0 1 1 0
1

1 0 0 1
0
1 1

 If both R and S are one, out could be either

zero or one.
 “quiescent” state -- holds its previous value
 note: if a is 1, b is 0, and vice versa

Introduction to Computing Systems and Programming Fall 1384, 29

 Clearing the R-S latch
 Suppose we start with output = 1, then
change R to zero.
1
0 1
1
1 Output changes to zero.
1 0
0 1
1 0
1

0 0
1
0

Introduction to Computing Systems and Programming Fall 1384, 30

 Setting the R-S Latch
 Suppose we start with output = 0, then
change S to zero.
1
1 0

0
Output changes to one.
1 1
0
0 1

1
1 0

Introduction to Computing Systems and Programming Fall 1384, 31

 R-S Latch
 R=S=1
 hold current value in latch
 S = 0, R=1
 set value to 1
 R = 0, S = 1
 set value to 0

 R=S=0
 both outputs equal one
 final state determined by electrical properties of gates

 Don’t do it!
Introduction to Computing Systems and Programming Fall 1384, 32
 Gated D-Latch

 Two inputs: D (data) and WE (write enable)

 when WE = 1, latch is set to value of D
 S = NOT(D), R = D
 when WE = 0, latch holds previous value
 S=R=1

Introduction to Computing Systems and Programming Fall 1384, 33

 Register
 A register stores a multi-bit value.
 We use a collection of D-latches, all controlled by a
common WE.
 When WE=1, n-bit value D is written to register.

Introduction to Computing Systems and Programming Fall 1384, 34

 Memory
 Now that we know how to store bits, we can build
a memory – a logical k × m array of stored bits.

Address Space:
k = 2n
number of locations locations •
(usually a power of 2) •
•

Addressability:
number of bits per location m bits
(e.g., byte-addressable)
Introduction to Computing Systems and Programming Fall 1384, 35
 Address Space

 n bits allow the addressing of 2n memory

locations.
 Example: 24 bits can address 224 = 16,777,216 locations
(i.e. 16M locations).
 If each location holds 1 byte then the memory is 16MB.
 If each location holds one word (32 bits = 4 bytes) then it
is 64 MB.

Introduction to Computing Systems and Programming Fall 1384, 36

 Addressability
 Computers are either byte or word addressable - i.e. each
memory location holds either 8 bits (1 byte), or a full standard
word for that computer (typically 32 bits, though now many
machines use 64 bit words).
 Normally, a whole word is written and read at a time:
 If the computer is word addressable, this is simply a single address
location.
 If the computer is byte addressable, and uses a multi-byte word, then the
word address is conventionally either that of its most significant byte (big
endian machines) or of its least significant byte (little endian machines).
Introduction to Computing Systems and Programming Fall 1384, 37
 Memory Structure A[1:0] D

WE
 Each bit
 is a gated D-latch
 Each location
 consists of w bits (here w = 1)
 w = 8 if the memory is byte
addressable
 Addressing
 n locations means log2n address
bits (here 2 bits => 4 locations)
 decoder circuit translates
address into 1 of n addresses

Introduction to Computing Systems and Programming Fall 1384, 38

 Memory example

A 22 by 3 bits memory:
•two address lines: A[1:0]
•three data lines: D[2:0]
•one control line: WE

One gated
D-latch

Introduction to Computing Systems and Programming Fall 1384, 39

 22 x 3 Memory
word select word WE input
address
bits
write
enable

address
decoder
Introduction to Computing Systemsoutput bits
and Programming Fall 1384, 40
 Memory details
 This is a not the way actual memory is implemented.
 fewer transistors, much more dense, relies on electrical properties
 But the logical structure is very similar.
 address decoder
 word select line
 word write enable
 Two basic kinds of RAM (Random Access Memory)
 Static RAM (SRAM)
 fast, maintains data without power
 Dynamic RAM (DRAM)
 slower but denser, bit storage must be periodically refreshed
Introduction to Computing Systems and Programming Fall 1384, 41
 Memory building blocks
– Building an 8K byte memory using chips that are 2K by 4 bits.
 CS = chip select:
A10-A0 2K x 4 bits 2K x 4 bits when set, it enables
CS CS the addressing,
reading and writing
d
2K x 4 bits 2K x 4 bits of that chip.
CS CS
e
A12-A11 c
o
d 2K x 4 bits 2K x 4 bits
er CS CS
This is an 8KB
byte addressable
2K x 4 bits 2K x 4 bits memory
CS CS

Introduction to Computing Systems and Programming Fall 1384, 42