Timing Diagram of 8085 Instructions

Prof. JAGADISH BHATTACHARYA.

ECE Dept. ,HETC

8/20/2019 1
Introduction:
 Timing diagram: Timing diagram is a graphical representation of
an instruction. In this diagram we use the clock signal as
reference signal. The other signals which are used to draw the
timing diagram are AD0- AD7, A8-A15, S0 & S1, IO/M`, ALE, RD`
and WR`. It consists of one or more than one machine cycles.
 Machine cycle: Machine cycle is the time required to complete
one operation-accessing either the memory or an I/O device. It
consists of 3to 6 T-states.
 T-state: The time corresponding to one clock period is called T-
state. It is the basic unit to calculate the program execution
time.
 Instruction cycle: The time taken by the processor to complete
the execution of an instruction. It consists of 1 to 6 machine
cycle. It is made up of fetch cycle (FC) and execution cycle (EC).

8/20/2019 2
Timing Diagram of STA instruction

8/20/2019 3
Explanation of STA instruction
 The “STA addr 16” instruction is used to store the content of the
accumulator to a memory location.
 STA is a 3-byte instruction. The first byte is the opcode (operational code)
of the instruction 32H. The second byte is the lower byte address 6AH and
the third byte is the higher byte address 52H.
 Let the three bytes of the instruction is stored in memory locations 41FFH,
4200H and It consists of four machine cycles and thirteen T-states.
 In each machine cycle at the first T-state ALE is asserted high, every time
the read signal is activated to read the data from the data bus. Depending
on the machine cycle the value of the status signals (S1 & S0) change.
 The four machine cycles are opcode fetch(F)[4T], memory read(R)
[3T], memory read(R) [3T] and memory write(W) [3T].
 In the opcode fetch machine cycle, the processor fetch the opcode of the
instruction and then do the execution.
 The two memory read cycles is used to read the memory address where
the content of accumulator will be stored.
 In the memory write machine cycle the content of PC (program counter)
changes to 526AH and the ACCUMULATOR content (C7H) is stored.

8/20/2019 4
Timing Diagram of PUSH instruction

8/20/2019 5
Explanation of PUSH instruction
 The “PUSH rp” instruction is used to store the content of a register pair
in the stack memory. It is a one byte instruction and it is the opcode of the
instruction.
 Here we consider PUSH B instruction. One execution of this instruction, the
content of the BC pair is pushed to the stack. Let the content of the BC pair be
E25DH and the content of SP be A100H.
 The opcode of PUSH B instruction is C5H and let it be stored in memory
location C010H.
 The PUSH instruction consists of three machine cycles and twelve T-states. The
machine cycles are: opcode super fetch(O)[6T], memory write(W)[3T] and
memory write(W)[3T].
 In the super fetch cycle the processor executes the opcode of the instruction
(C5H) and the two memory write cycles are used to store the content of BC
pair.
 During the first memory write cycle, the content of the SP is decremented by
one (A100H -1= A0FFH) and at this address the content of B-register (E2H) is
stored.
 In the second memory write cycle, the content of the SP is again decremented
by one (A0FFH -1= A0FEH) and at this address the content of C-register (5DH)
is stored.

8/20/2019 6
Timing Diagram of IN instruction

8/20/2019 7
Explanation of IN instruction
 The “IN addr8” instruction is used to read the content of an I/O
mapped device/ port and then to write the data into the
accumulator.
 The IN instruction is a two byte instruction. The first byte is the opcode of
the instruction (DBH) and the second byte is the I/O port address (COH).
 Let the two bytes of the instruction be stored in memory locations 4125H
and 4126H.
 The IN instruction consists of three machine cycles which are opcode
fetch(F)[4T], memory read(R) [3T] and I/O read(I) [3T] total 10
T-states.
 In the first machine cycle, the opcode DBH is fetched from the memory
(4125H), placed in the instruction register, and decoded.
 During the second machine cycle, the port address COH is read from the
next memory location (4125H).
 In the third machine cycle, the address COH is placed in the address bus
and the data is read from the port and placed in the accumulator.

8/20/2019 8
Timing Diagram of OUT instruction

8/20/2019 9
Explanation of OUT instruction
 The “OUT addr8” instruction is used to send the content of
the accumulator to the I/O mapped device/ port.
 The OUT instruction is a two byte instruction. The first byte is the
opcode of the instruction (D3H) and the second byte is the I/O
port address (83H).
 Let the two bytes of the instruction be stored in memory locations
40FFH and 4100H.
 The OUT instruction consists of three machine cycles which are
opcode fetch(F)[4T], memory read(R) [3T] and I/O write(O)
[3T] total 10 T-states.
 In the first machine cycle, the opcode D3H is fetched from the
memory (40FFH), placed in the instruction register, and decoded.
 During the second machine cycle, the port address 83H is read
from the next memory location (4125H).
 In the third machine cycle, the address 83H is placed in the address
bus and the data is read from the accumulator and placed in the
port.

8/20/2019 10
Timing Diagram of INR M instruction

8/20/2019 11
Explanation of INR M instruction
 The “INR M” instruction is used to increment the content of a memory
location.
 INR M is an one-byte instruction and its opcode is 34H. It consists of three
machine cycles and 10 T-states. The three machine cycles are opcode
fetch(F)[4T], memory read(R) [3T] and memory write(W) [3T].
 Let the content of the HL pair be 4250H and let the content of the memory
location 4250H be 12H.
 The memory content cannot be changed in the memory location itself. It has
to be read into the processor and then modified. After modification, it has to
be written into the same memory address. Therefore, this instruction requires
three machine cycles.
 During the first machine cycle, the opcode (34H) is fetched from the memory
(4105H).
 In the second machine cycle, the contents of the HL(4250H) are placed in the
address bus, the memory content is brought to the processor, and its value is
incremented (13H) .
 During the third machine cycle, the incremented data is again written back into
the same address (4250H).

8/20/2019 12
Timing Diagram of CALL instruction

8/20/2019 13
Explanation of CALL instruction
 The “CALL addr 16” instruction is used to execute a subroutine stored at addr 16,
after saving the address of the next instruction in the stack memory.
 It is a three byte instruction. The first byte is the opcode of the instruction CDH. The
second byte is the lower order address 50H and the third byte is the higher order address
4FH.
 The CALL instruction consists of five machine cycles and eighteen T-states.The machine
cycles are: opcode super fetch(O)[6T], memory read(R) [3T], memory read(R) [3T],
memory write(W)[3T] and memory write(W)[3T].
 Let the three bytes of the instructions be stored in memory locations 4200H, 4201H and
4202H. Also let the address of the subroutine be 4F50H and the content of the SP be
4100H.
 During the first machine cycle the opcode (CDH) of the instruction is fetch, in the second
and third machine cycles (memory read cycles) the processor read the second and third
bytes of the instruction (read the address of the subroutine).
 At the end of the memory read cycle, the content of the PC will be 4203H. After the two
memory read cycles the processor executes the two memory write cycles to store the
content of PC in the stack.
 In the first memory write cycle, the content of the SP is decremented by one
(A100H -1= A0FEH) and at this address the content of PCH (42H) is stored.
 In the second memory write cycle, the content of the SP is again decremented by one
(A0FFH -1= A0FEH) and at this address the content of PCL (03H) is stored.

8/20/2019 14
Timing Diagram of RET instruction

8/20/2019 15
Explanation of RET instruction
 In a program, while calling a subroutine using CALL instruction, the
address of the next instruction of the program is stored in the top of the
stack. On execution of the “RET” instruction, the top of the stack is loaded
in PC (Program Counter).
 Let the content of SP (Stack Pointer) be 40FEH and the content of the
stack memory locations 40FEH and 40FFH be 03H and 42H respectively.
 The RET instruction is a one byte instruction and its opcode is C9H. Let
the instruction is stored in the memory location 4F80H.
 RET is a three byte instruction. It consists of three machine cycles and ten
T-states
 The four machine cycles are opcode fetch(F)[4T], memory read(R) [3T],
memory read(R) [3T] and memory write(W) [3T].
 During the second machine cycle, the content of the SP (40FEH) is used as
the memory address. The memory content (03H) is read and store in the
PCL (program counter low).
 In the third machine cycle, the content of SP is incremented by one (40FEH
+1 = 40FFH) and at this memory content (42H) is read and stored in PCH.

8/20/2019 16
Bibliography:

1. Ramesh Gaonkar,“Microprocessor Architecture,

Programming, and Applications with 8085”, Fifth Edition,
Penram International Publishing, Mumbia, 2005.
2. A. Nagoor Kani, “Microprocessor and Microcontroller”,
Second Edition, Tata McGraw Hill, New Delhi, 2012.
3. N. Senthil Kumar, M.Saravanan and S.Jeevananthan,
“Microprocessor and Microcontroller”, First Edition, Oxford
University Press, New Delhi, 2011.

8/20/2019 17
8/20/2019 18