synchronization

synchronize
• Synchronization is needed to know when it is safe for
different processes to use shared data.
• Issues for synchronization
– Uninterruptable instruction to fetch and update
memory( atomic operation)
– User level synchronization using this primitive
– For large mp synchronization is bottleneck .
techniques to reduce contention and latency of
synchronization
• Basic synchronization operations

– Atomic exchange

– Test and set

– Fetch and increment

 Atomic exchange

Atomic exchange will interchange a value in a register for a

value in memory

0=> synchronization variable is free

1=> synchronization variable is locked and unavailable

Set register to 1 and swap

New value in register determine success in getting lock

0 if you succeeded in setting the lock

1 if other processor had already claimed access.

• Test and set
– Test and set is used to tests a value and sets it if the
values passes the test.
Fetch and increment
 Fetch and increments returns the value of a
memory location and atomically increments it.
 0=> synchronization variable is free
Atomic read and update operation:
Requires both a memory read and a write in a
single uninterruptable instructions.
Cannot allow any other operations between the read
and write.
 Solution(load-linked and store
conditional)
• Load linked or load locked
• A special store called a store conditional
Sequence instruction
If the contents of the memory location specified
by the load linked are changed before rthe store
conditional to the same address.
 Spin Locks
• Spin locks are the locks that a processor
continuously tries to acquire, spinning around a
loop until it succeeds.
• The coherence mechanism of a multiprocessors
are used to implement spin locks.
• Spin locks are used when
– Lock to be held for a very short amount of time
– Process of locking to be low latency when the lock is
available.
 Models of Memory Consistency
• Processor 1: Processor 2:
A=0 B=0
… …
A=1 B=1
if (B==0) … if (A==0) …
Result of execution should be the same as long as:
• Accesses on each processor were kept in order
• Accesses on different processors were arbitrarily
interleaved
 Memory Consistency

Def: A memory consistency model for a shared address space specifies

constraints on the order in which memory operations must appear to be
performed (i.e. to become visible to the processors) with respect to one
another.

P1 P2 (A, flag are zero initial)

A=1 while(flag == 0);
flag=1 print A;
 Sequential Consistency
Sequential Consistency) “A multiprocessor is sequentially consistent if the
result of any execution is the same as if the operations of all the processors
were executed in some sequential order, and the operations of each
individual processor occur in this sequence in the order specified by its
program.”
 Processor Consistency
1. Before a read is allowed to perform with respect to any other processor, all
previous read must be performed and
2. Before a write is allowed to performed with respect to any other processor all
previous accesses(reads and writes) must be performed

• The above conditions relax sequential consistency by allowing reads following a a

write to bypass the write;
• Writes from the same processor should be observed in program order;