Beruflich Dokumente
Kultur Dokumente
11100111
11011101
00111001
10101001
10101010
• Checksum
– Used by upper layer protocols
– Similar to LRC, uses one’s complement
arithmetic
Winter 2005 ECE 766 10 - 4
Computer Interfacing and Protocols
ECE
Cyclic Redundancy Check
• Powerful error detection scheme
• Rather than addition, binary division is
used Finite Algebra Theory (Galois
Fields)
• Can be easily implemented with small
amount of hardware
– Shift registers
– XOR (for addition and subtraction)
k bits n bits
• Associate bits with coefficients of a
polynomial
1 0 1 1 0 1 1
1x6+0x5+1x4+1x3+0x2+1x+1
= x6+x4+x3+x+1
• Receiving
1. Receive F’(x)
2. Divide F’(x) by P(x)
3. Accept if remainder is 0, reject otherwise
Remainder 0 Remainder 0
Note: Binary modular addition is equivalent to
binary modular subtraction C(x)+C(x)=0
Winter 2005 ECE 766 10 - 9
Computer Interfacing and Protocols
ECE
Example
• Send • Receive
– M(x) = 110011 x5+x4+x+1 (6 bits)
– P(x) = 11001 x4+x3+1 (5 bits, n = 4) 11001 1100111001
4 bits of redundancy
11001
– Form xnM(x) 110011 0000
x9+x8+x5+x4 11001
– Divide xnM(x) by P(x) to find C(x)
11001
100001 00000
11001 1100110000
11001 No remainder
10000 Accept
11001
1001 = C(x)
Send the block 110011 1001
Winter 2005 ECE 766 10 - 10
Computer Interfacing and Protocols
ECE
Properties of CRC
• Sent F(x), but received F’(x) = F(x)+E(x)
Proof:
Assume an odd number of errors has x+1 as a factor.
Then E(x) = (x+1)T(x).
Evaluate E(x) for x = 1
E(x) = E(1) = 1 since there are odd number of terms
(x+1) = (1+1) = 0
(x+1)T(x) = (1+1)T(1) = 0
E(x) ≠ (x+1)T(x)
Message
1 1100
0011
0100
0000 0000
0111 1 1000
0000 1000
1110 0 1101
1101 1010
0110 0010
1 0000
0000 0100
1100 1100
1101 1 1101
001 001
Winter 2005 ECE 766 10 - 16
Computer Interfacing and Protocols
ECE
Hardware Implementation
Transmit:
Data SQ Bit 2 Bit 1 Bit 0
MSB
1 1 0 0 0
Serial Quotient (SQ) 0 1 1 0 1
Message
x3 x2 1 0 1 1 1
x0 1 0 1 1 0
+ 2 + 1 0 0 1 1 0 0
1 0 1 0 1
Data
1 1 0 1 0
LSB
Input 0 0 1
CRC
k shifts later, CRC is in register Send MSB first
Shift out (without any XOR) in n shifts
Message
x3 x2 1 0 1 1 1
x0 1 0 1 1 0
+ 2 + 1 0 0 1 1 0 0
1 0 1 0 1
Data
1 1 0 1 0
LSB
Input
MSB
0 0 0 0 1
CRC 0 0 0 1 0
n+k shifts later, remainder is 0 1 0 1 0 0
Data accepted 0 0 0
LSB
+ 2
1 0
Data In
A
Control Line A:
A 1: Make/Test CRC
0: Shift Out CRC
Data OK
For Transmitting:
Data Out Assert A true while feeding k bits of message
Assert A false for n clock cycles to output CRC
For Receiving:
A Assert A true while feeding k+n bits of message and CRC
Ignore Data Out, check Data OK for correctness