Arria 10 HPS External

Memory Interface
Guidelines
Quartus Prime Software v17.0
Introduction

 This slide deck covers the following topics:

– HPS EMIF limitations/restrictions
– HPS EMIF IP generation
– HPS EMIF pin constraints
*EMIF = External Memory Interface

2
Software Requirements

 Quartus Prime Software v17.0

3
HPS EMIF Overview

 HPS EMIF supports:

– Half-rate interfaces
– Interface widths of 16, 32, and 64 (without ECC)
– Interface widths of 24, 40, and 72 (with ECC)
– x8 data groups
– DDR3 and DDR4

 HPS EMIF does not support:

– Ping-Pong PHY
– EMIF Debug Toolkit
– Quad-rank interfaces
– LRDIMM memory formats

4
Creating a Quartus Prime Project

The following slides demonstrate how to create a Quartus Prime

project
 Starting with Quartus Prime v17.0, users must create a Quartus
Prime project before generating the EMIF IP and accompanying
example design project New Project Wizard

1. Launch Quartus Prime and select New Project Wizard

– Or File > New Project Wizard

2. Press Next, select a directory and name /data/dabdulra/hps_emif_example

for the project, and select Next
hps_emif_example

5
Creating a Quartus Prime Project

3. Select Empty project and continue

to press Next until you reach the
Family, Device, and Board Settings
option
4. Select Arria 10 (GX/SX/GT) under
Family and then select your specific
Arria 10 device under Available
devices
– You can filter the available devices list
using the options on the right,
including the Name filter

5. Press Finish

6
Generating the HPS EMIF IP

The following slides demonstrate how to generate the HPS EMIF IP

– For more information on how to do this, refer to slides 6-7

1. Launch Qsys:
– Tools > Qsys

2. Create a new Qsys system

7
Generating the HPS
EMIF IP
3. Click on the IP Catalog tab in the
top-left corner
– If the IP Catalog is not visible:
View > IP Catalog

4. Select Processors and Peripherals >

Hard Processor Components
5. Double-click Arria 10 External
Memory Interfaces for HPS

8
HPS EMIF Pin Guidelines

The following slides cover pin placement restrictions for HPS EMIF systems
 Arria 10 SoC devices have 3 modular I/O banks (2K, 2J, and 2I)
– Allows connection to a Hard Processor System (HPS)

 For systems using HPS EMIF:

– Only Banks 2K, 2J, and 2I can be used
– These banks can be used as FPGA GPIO when there is no HPS EMIF in the system
– Top bank is reserved for Address/Command pins

– Unused lanes can be used as FPGA inputs/outputs

– Unused pins in lanes used for data/ECC can be used as FPGA inputs only

 Users of SDRAM for HPS must instantiate the HPS EMIF in Qsys
– This allows the right banks/lanes to be assigned for the SDRAM I/O

9
HPS EMIF Pin
Constraints
 Design intent for Bank 2K when With/Without ECC
using HPS EMIF:

Lane 0 Lane 1 Lane 2 Lane 3

ECC
– Lane 3 is used for ECC for SDRAM
– Unused pins in this lane may be used Address/Command
as FPGA inputs only, regardless Bank 2K
whether ECC is enabled Address/Command

– The remaining lanes are used for Address/Command

Address/Command
– Unused pins in these lanes (0-2) may
Pins not dedicated for
be used as FPGA inputs/outputs
ECC can be used as
FPGA
inputs only

10
HPS EMIF Pin Constraints
x16 Interface
 Design intent for Bank 2J when

Lane
FPGA GPIO

3
using HPS EMIF:

Lane
FPGA GPIO

2
– Bank 2J is used for data bits Bank 2J Pins not

Lane
Data used for

1
[31:0] data can
be used as

Lane
– With a 16-bit interface, unused Data FPGA

0
inputs only
pins in the lanes used for data
can be used as FPGA inputs only x32 Interface
– Pins in the unused lanes can

Lane
Data

3
be used as FPGA
Pins not
inputs/outputs

Lane
Data used for

2
data can
– With a 32-bit interface, unused Bank 2J be used as

Lane
pins can be used as FPGA inputs Data FPGA

1
inputs only
only

Lane
Data

0
– Specific lanes used for data vary
depending on device package 11
HPS EMIF Pin Constraints
x16 or x32 Interface
(located in Bank 2J)
 Design intent for Bank 2I when using

Lane
FPGA GPIO

3
HPS EMIF:

Lane
FPGA GPIO

2
– Bank 2I is used for data bits [63:32] Bank 2I

Lane
– With a 16-bit or 32-bit interface, this FPGA GPIO

1
bank can be used as FPGA

Lane
inputs/outputs GPIO

0
– With a 64-bit interface, unused pins
can be used as FPGA inputs only
x64 Interface
– Not all devices contain Bank 2I

Lane
Data

3
Pins not

Lane
Data used for

2
data can
Bank 2I be used as

Lane
Data FPGA

1
inputs only

Lane
Data

0
12