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PRESENTATION
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 CONTENTS
INTRODUCTION

CHARACTERIZATION OF DAC
(a) STATIC CHARACTERISTICS
(b) DYNAMIC CHARACTERISTICS

TESTING OF DACs

CLASSIFICATION OF DACs
(a)PARALLEL DACs
(b)SERIAL DAC

APPLICATIONS
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 INTRODUCTION
The most important functions in signal processing is the conversion of Analog and Digital
signals.

Signal processing is done on both analog and digital signals.

It is necessary to convert back and forth between the two types of signals.

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The DAC is presented first because it is generally part of an ADC.

The DAC consists of - Comparators

- Digital Circuitry

- Switches

- Integrators

- Sample and Hold circuit

- Operational Amplifiers

- Voltage Reference
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b0 is the most significant bit (MSB)
The MSB is the bit that has the most (largest) influence on the analog output

bN-1 is the least significant bit (LSB)

The LSB is the bit that has the least (smallest) influence on the analog output
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The output voltage Vout can be expressed as:

Vout = KVref.D
K is the Scaling factor,
D is the digital word given as:

N is the total number of bits of the digital word.

Therefore the output of DAC can be written as:

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 STATIC CHARACTERISTICS

Fig: Ideal Input-Output

characteristic of 3-bit DAC

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RESOLUTION : Resolution of the DAC is equal to the number of bits in the applied
digital input word.

It is expressed as N bits, where N is the number of bits.

Each of the eight possible digital words has its own analog output voltage which are
separated by an LSB.

With an increase in digital word by 1-bit, output of DAC should jump by 1 LSB.

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 Poor Resolution(1 bit) Better Resolution(3 bit)

Vout Vout

Desired Analog signal Desired Analog signal

111
110
110
1
2 Volt. Levels

101 101

8 Volt. Levels
100 100

011 011

010 010

001 001

0 0 000
000
Digital Input
Approximate output Approximate output Digital Input

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FULL SCALE (FS): Because the resolution of DAC is finite (3 in case of Fig.), the
maximum analog output voltage does not equal to Vref. This is characterized by the Full
Scale value of DAC.

Full Scale value is the difference between the analog output for the largest digital word
(1111….) and the analog output for the smallest digital word (000….).

Full scale range (FSR) is defined as:

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QUANTIZATION NOISE : It is the inherent uncertainty in digitizing an analog value with
a finite resolution converter.

Fig: Quantization Noise for 3-bit DAC

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Quantization Noise is equal to the analog output of infinite bit DAC minus the analog
output of the finite bit DAC.

It is the fundamental property of DACs and represents the limit of accuracy of converters.

DYNAMIC RANGE (DR) : Dynamic Range of a DAC is the ratio of the FSR to the
smallest difference that can be resolved (i.e. an LSB).

or in terms of decibels

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The DR is the amplitude range necessary to resolve N bits regardless of the amplitude of
the output voltage.

When referenced to a given output analog signal amplitude, the DR required must
include 1.76 dB more to account for the presence of quantization noise.

For a 10-bit DAC, the DR is 60.2 dB and for a full-scale, rms output voltage, the
signal must be approximately 62 dB above whatever noise floor is present in the output
of the DAC.

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SIGNAL-TO-NOISE RATIO (SNR) : SNR for the DAC is the ratio of the full scale
value to the rms value of the quantization noise.

rms (quantization noise) =

Maximum SNR for a sinusoid is defined as:

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Effective number of bits (ENOB) can be defined from the above as:

Where is the actual SNR of the converter.

For each digital word , there should be a unique analog output signal. Any deviation that
occurs falls in the category of static- conversion errors.

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 STATIC CONVERSION ERRORS
Static Conversion Errors include: (a) OFFSET ERRORS

(b) GAIN ERRORS

(c) INTEGRAL NONLINEARITY

(d) DIFFERENTIAL NONLINEARITY

(e) MONOTONICITY

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OFFSET ERROR:

An offset error is a constant difference between the actual finite resolution characteristic and
the ideal finite resolution characteristic measured at any vertical jump.

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GAIN ERROR :

A gain error is the difference between the slope of the actual finite resolution and the ideal
finite resolution characteristic measured at the right-most vertical jump.

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INTEGRAL NONLINEARITY:

Integral Nonlinearity (INL) is the maximum difference between the actual finite resolution
characteristic and the ideal finite resolution characteristic measured vertically (% or LSB).

It can be expressed in terms of FSR or LSB.

DIFFERENTIAL NONLINEARITY:

Differential Nonlinearity (DNL) is a measure of the separation between adjacent levels

measured at each vertical jump (% or LSB).It measures bit to bit deviations from ideal output
steps.

where Vcx is the actual voltage change on a bit-to-bit basis and Vs is the ideal LSB change
of 13(VFSR/2N).
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MONOTONOCITY : In DAC it means that as the digital input to the converter increases
over its FSR , the analog output never exhibits a decrease between one conversion step and
the next.

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 DYNAMIC CHARACTERISTICS
Dynamic characteristics include the influence of time.

CONVERSION SPEED : It is the time it takes for the DAC to provide an analog output
when the digital input word is changed.

Factors that determine the conversion speed of DAC :

- Parasitic Capacitors
- Op-amp Gain Bandwidth
- Op-amp Slew Rate

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GAIN ERROR : Gain error of an op-amp is the difference between the desired and actual
output voltage of the op-amp.

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 TESTING OF DACs
INPUT-OUTPUT TEST:

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Sweep the digital input word from 000...0 to 111...1.

The ADC should have more resolution by at least 2 bits and be more accurate than the
errors of the DAC.

INL will show up in the output as the presence of 1’s in any bit. If there is a 1 in the Nth
bit, the INL is greater than ±0.5LSB

DNL will show up as a change between each successive digital error output. The bits
which are greater than N in the digital error output can be used to resolve the errors to less
than ±0.5LSB.

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SPECTRAL TEST :

Digital input pattern is selected to have a fundamental frequency which has a magnitude
of at least 6N dB above its harmonics.

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Length of the digital sequence determines the spectral purity of the fundamental frequency.

All nonlinearities of the DAC (i.e. INL and DNL) will cause harmonics of the fundamental
frequency.

Decrease in the period of digital pattern causes an increase in the effective signal frequency.

The noise floor of the spectral output will increase due to frequency dependence of the
DAC.

SNR determines from this measurement gives the Effective no. of Bits (ENOB).

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CLASSIFICATION OF DIGITAL–ANALOG CONVERTERS

DACs can be categorized by:

(a) how long it takes to perform conversion

(b) how the binary scaling of the reference is accomplished

(c) Scaling methods - (1) Current Scaling

(2) Voltage Scaling

(3) Charge Scaling

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PARALLEL DIGITAL – ANALOG CONVERTERS
CURRENT SCALING DIGITAL-ANALOG CONVERTERS:

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The output voltage can be expressed as :

VOUT = -Rf(I0 + I1 + I2 + ··· + IN-1)

where the currents I0, I1, I2, ... are binary weighted currents and Rf is the feedback
resistance.
Rf can be used to scale the gain of the DAC. If Rf = KR/2, then,

where bi is 1 if switch Si is connected toVref or 0 if switch Si is connected to ground.

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BINARY-WEIGHTED RESISTOR DAC :

Attributes:

Insensitive to parasitic capacitors and hence fast.

Large component spread value leads to poorer matching between resistors.

Nonmonotonic.
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 Component Spread Value =

R-2R LADDER IMPLEMENTATION OF THE BINARY WEIGHTED RESISTOR

DAC

The R-2R Ladder concept is used to avoid large element spread values.

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Attributes:

Not sensitive to parasitic capacitances.

(currents through the resistors never change as Si is varied)

Small element spread. Resistors made from same unit (2R consist of two in series or R
consists of two in parallel).

Not monotonic.

How does the R-2R ladder work?

The resistance seen to the right of any of the vertical 2R resistors is 2R.

This reduces the current by a factor of 2 as it flows from leftmost vertical 2R to rightmost
vertical 2R.
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CURRENT SCALING USING BINARY WEIGHTED MOSFET CURRENT SINKS:

Attributes:

Fast and not monotonic.

Accuracy
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If , then,

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VOLTAGE SCALING DIGITAL-ANALOG CONVERTERS:

Creates all possible values of the analog output then uses a decoding network to
determine which voltage to select based on the digital input word.

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3-BIT VOLTAGE SCALING DIGITAL-ANALOG CONVERTER:

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The voltage at any tap can be expressed as:

Attributes:

• Guaranteed monotonic
• Compatible with CMOS technology
• Large area if “ n ” is large
• Sensitive to parasitic
• Requires a buffer
• Large current can flow through the resistor string.

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Alternate Realization of the 3-Bit Voltage Scaling DAC:

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CHARGE SCALING DACs:

 It operate by binarily dividing the total charge applied to a capacitor array.

 This process is implemented by using capacitors to attenuate the reference voltage as

shown in fig below.

Fig:- General charge scaling DAC.

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• Fig:- Charge scaling DAC. Switches are connected to ground during ф1. Switch Si closes to bi =
1 or to ground if bi = 0 during ф2.

Fig:- Equivalent circuit of above figure.

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 Calculated as if the capacitors were resistors. For example,

 All switches are connected to ground during ф1.

 Switch Si closes to VREF if bi = 1 or to ground if bi = 0.
Equating the charge in the capacitors gives,

which gives,

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Attributes:
• Accurate.
• Sensitive to parasitic.
• Not monotonic.
• Charge feed through occurs at turn on of switches.

Summary of the performance of parallel DACs:

DAC Type Advantage Disadvantage

Current Scaling Fast, insensitive to parasitics Large element spread,

Voltage Scaling
Charge Scaling
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nonmonotonic
Monotonic, equal resistors Large area, sensitive to parasitic
capacitance
Fast, good accuracy Large element spread,
nonmonotonic
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EXTENDING THE RESOLUTION OF PARALLEL DACs:

 A common problem in the parallel DAC implementation is the area required as the
resolution of the DAC becomes large.

 Considering the area required, the ratio of the value of the MSB component to the
value of the LSB component becomes large.

 The first approach combines DACs using similar scaling methods.

 The second approach combines the various scaling approaches in an attempt to get the
best characteristics of each scaling approach.

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Technique:
Divide the total resolution “N” into “k” smaller sub - DACs each with a resolution of
“N/k”.

Result:
Smaller total area.
More resolution because of reduced largest to smallest component spread.

Approaches:
Combination of similarly scaled DACs.
Divider approach (scale the analog output of the sub DACs)
Sub-ranging approach (scale the reference voltage of the sub DACs)
Combination of differently scaled DACs.
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COMBINATION OF SIMILARLY SCALED DACs:

Example of combining m - bit and k - bit sub DAC to form a (m+k) bit DAC.

Fig:- Combining an m-bit & k-bit subDAC to form an (m + k) bit DAC by dividing
the output of the k-LSB DAC.
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 Here, we will consider that two subDACs use the same scaling method. One subDAC
converts the M-MSB bits & the other DAC converts the K-LSB bits.

 The analog output of the LSB DAC is divided by to scale it properly.

 The analog output of the combined subDACs can be written as;

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 REFERENCE SCALING - SUBRANGING APPROACH:

 Another method of combining two or more DACs is to increase is shown in

figure below.

 Here instead of scaling the output of the sub DACs, the voltage to each subDAC
is scaled.

 This method of combining subDACs is called subranging.

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 Fig:- Combining an m-bit & k-bit subDAC to form an (m + k) bit DAC by dividing the VREF to
the k-LSB DAC (subranging).

 The analog output of the subranging DAC can be expressed as:

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COMBINATION OF DIFFERENTLY SCALED DACs:

 The second approach to extending the resolution of parallel DACs uses subDACs
having different scaling methods.

Fig:- (m + k) bit DAC using an m-bit voltage scaling subDAC for the MSBs and a
k-bit charge scaling subDAC for the LSB.
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 Operation:

 Switches “SF” and “S1B” through “Sk,B” discharge all capacitors.

 Decoders A and B connect Bus A and Bus B to the top and bottom, respectively, of the
appropriate resistor as determined by the m-bits.
 The charge scaling subDAC divides the voltage across this resistor by capacitive
division determined by the k-bits.

 Advantages:

 The MSBs are guaranteed to be monotonic.

 The accuracy of the LSB is greater than the MSBs because they are determined by
capacitors.

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 SERIAL DIGITAL-ANALOG CONVERTERS
SERIAL DACS:

 Typically require one clock pulse to convert one bit.

 Types considered here are:
(a) Charge-redistribution.
(b) Algorithmic.

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 Operation:

 Switch S1 is the redistribution switch that parallels C1 and C2 sharing their charge.
 Switch S2 recharges C1 to VREF if the bit, bi is a 1.
 Switch S3 discharges C1 to zero if the bit, bi, is a 0.
 Switch S4 is used at the beginning of the conversion process to initially discharge C2.
 Conversion always begins with the LSB bit and goes to the MSB bit.

 Note:

 Serial charge redistribution in DAC is simple and requires minimum area but is slow and
requires complex external circuitry.

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 COMMON APPLICATIONS

 Generic use.

 Circuit Components.

 Digital Audio.

 Function Generators / Oscilloscopes.

 Motor Controllers.

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GENERIC:

 Used when a continuous analog signal is required.

 Signal from DAC can be smoothed by a Low pass filter.

Piece-wise Continuous Analog Continuous

Digital Input Output Output
0 bit

011010010101010100101
101010101011111100101
000010101010111110011
010101010101010101010
n bit DAC Filter
111010101011110011000
100101010101010001111

nth bit

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CIRCUIT COMPONENTS:

 Voltage controlled Amplifier.

– digital input, External Reference Voltage as control.

 Digitally operated attenuator.

– External Reference Voltage as input, digital control.

 Programmable Filters.
– Digitally controlled cutoff frequencies.

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DIGITAL AUDIO

 CD Players.
 MP3 Players.
 Digital Telephone / Answering Machines.

1 2 3

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FUNCTION GENERATORS

 Digital Oscilloscopes.  Signal Generators.

– Digital Input – Sine wave generation
– Analog Output – Square wave generation
– Triangle wave generation
– Random noise generation

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MOTOR CONTROLLERS

1
 Cruise Control
 Valve Control
 Motor Control

3
2

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