IMPLEMENTATION OF UART

AND ETHERNET USING FPGA

SRI HARSHA VELLATURI
REG NO : 1210416154
FPGA

 A field-programmable gate array (FPGA) is an integrated circuit designed to be configured by a customer

or a designer after manufacturing – hence the term "field-programmable". The FPGA configuration is
generally specified using a hardware description language (HDL), similar to that used for an Application-
Specific Integrated Circuit (ASIC). Circuit diagrams were previously used to specify the configuration, but
this is increasingly rare due to the advent of electronic design automation tools.
 FPGAs contain an array of programmable logic blocks, and a hierarchy of "reconfigurable interconnects"
that allow the blocks to be "wired together", like many logic gates that can be inter-wired in different
configurations. Logic blocks can be configured to perform complex combinational functions, or merely
simple logic gates like AND and XOR. In most FPGAs, logic blocks also include memory elements, which
may be simple flip-flops or more complete blocks of memory. Many FPGAs can be reprogrammed to
implement different logic functions, allowing flexible reconfigurable computing as performed in computer
software.
VIVADO SOFTWARE

 VIVADO Design Suite is a software suite produced by Xilinx for synthesis and analysis of
HDL designs, superseding Xilinx ISE with additional features for system on a chip
development and high-level synthesis. VIVADO represents a ground-up rewrite and re-
thinking of the entire design flow (compared to ISE), and has been described by reviewers as
"well-conceived, tightly integrated, blazing fast, scalable, maintainable, and intuitive".

 Like the later versions of ISE, VIVADO includes the in-built logic simulator ISIM. VIVADO
also introduces high-level synthesis, with a tool chain that converts C code into
programmable logic. VIVADO has been described as a "state-of-the-art comprehensive EDA
tool with all the latest bells and whistles in terms of data model, integration, algorithms, and
performance
UART

 A universal asynchronous receiver-transmitter (UART) is a computer hardware device

for asynchronous serial communication in which the data format and transmission
speeds are configurable. The electric signaling levels and methods are handled by
a driver circuit external to the UART. A UART is usually an individual (or part of an)
integrated circuit (IC) used for serial communications over a computer or peripheral
device serial port. One or more UART peripherals are commonly integrated in
microcontroller.
TRANSMITTER

 The universal asynchronous receiver-transmitter (UART) takes bytes of data and transmits
the individual bits in a sequential fashion. At the destination, a second UART re-assembles
the bits into complete bytes. Each UART contains a shift register, which is the fundamental
method of conversion between serial and parallel forms. Serial transmission of digital
information (bits) through a single wire or other medium is less costly than parallel
transmission through multiple wires.

 The UART usually does not directly generate or receive the external signals used between
different items of equipment. Separate interface devices are used to convert the logic
level signals of the UART to and from the external signaling levels, which may be
standardized voltage levels, current levels, or other signals.
DATA FRAMING

 The idle, no data state is high-voltage, or powered. This is a historic legacy from telegraphy, in which the
line is held high to show that the line and transmitter are not damaged. Each character is framed as a logic
low start bit, data bits, possibly a parity bit and one or more stop bits. In most applications the least
significant data bit (the one on the left in this diagram) is transmitted first, but there are exceptions (such as
the IBM 2741 printing terminal).
 The start bit signals the receiver that a new character is coming. The next five to nine bits, depending on
the code set employed, represent the character. If a parity bit is used, it would be placed after all of the data
bits. The next one or two bits are always in the mark (logic high, i.e., '1') condition and called the stop
bit(s). They signal to the receiver that the character is complete. Since the start bit is logic low (0) and the
stop bit is logic high (1) there are always at least two guaranteed signal changes between characters.
 If the line is held in the logic low condition for longer than a character time, this is a break condition that
can be detected by the UART.
BASICS OF SERIAL COMMUNICATION

Bit rate:-

Number of bits sent every second (BPS).

Baud rate:-
Number of symbols sent every second, where every symbol can represent more than one bit.
Ex. high-speed modems which use phase shifts to make every data transition period represent
more than one bit.
For the PIC 16f877A’s USART, with every clock tick one bit is sent, each symbol represents one
bit.
So, we can consider bit rate and baud rate the same thing.
RECEIVER

 All operations of the UART hardware are controlled by an internal clock signal which runs at a multiple of the data
rate, typically 8 or 16 times the bit rate. The receiver tests the state of the incoming signal on each clock pulse,
looking for the beginning of the start bit. If the apparent start bit lasts at least one-half of the bit time, it is valid and
signals the start of a new character. If not, it is considered a spurious pulse and is ignored. After waiting a further
bit time, the state of the line is again sampled and the resulting level clocked into a shift register. After the required
number of bit periods for the character length (5 to 8 bits, typically) have elapsed, the contents of the shift register
are made available (in parallel fashion) to the receiving system. The UART will set a flag indicating new data is
available, and may also generate a processor interrupt to request that the host processor transfers the received data.

 Communicating UARTs usually have no shared timing system apart from the communication signal. Typically,
UARTs resynchronize their internal clocks on each change of the data line that is not considered a spurious pulse.
Obtaining timing information in this manner, they reliably receive when the transmitter is sending at a slightly
different speed than it should. Simplistic UARTs do not do this, instead they resynchronize on the falling edge of
the start bit only, and then read the center of each expected data bit, and this system works if the broadcast data rate
is accurate enough to allow the stop bits to be sampled reliably.

 It is a standard feature for a UART to store the most recent character while receiving the next. This "double
buffering" gives a receiving computer an entire character transmission time to fetch a received character. Many
UARTs have a small first-in, first-out FIFO buffer memory between the receiver shift register and the host system
interface. This allows the host processor even more time to handle an interrupt from the UART and prevents loss of
received data at high rates.
 IMPLEMENTATION PROCESS OF UART

The Board used is Kintex-7.

 Open the VIVADO software and click on “create project” which will launch the “create a new VIVADO project”
wizard.
 Clicking on next will take you to the next step of the process which is giving a name and location to the project.
 After assigning name and location the wizard will ask to select the type of project.
There are five different project types. They are:
RTL Project
Post-synthesis Project
I/O Planning Project
Imported Project
Example Project
Each type has its own specifications, design process, analysis and formats.
 Select RTL project and proceed. The next step will be in selecting the name of the project to be the module name
which is entirely based on the user.
 Click on finish and the setup will be completed. Now a new window opens regarding the design of the project.
 On the left-hand side there will a box named sources. From that box select the name of the project and a new
window will appear which will allow the user to write the Verilog code of the desired design.
 After entering the code, save it. Now from the project manager select the option “run simulation”.
 If the code has a test bench then the constraints are predefined or else the constraints are entered manually with the
code.
 After the code is simulated the simulated design goes under synthesis. Synthesis is the process of
transforming an RTL-specified design into a gate-level representation. VIVADO Integrated Design
Environment (IDE) synthesis is timing-driven and optimized for memory usage and performance. VIVADO
synthesis supports System Verilog as well as mixed VHDL and Verilog languages.
 After synthesis the design is converted into gate level where it is at a point where it can be converted into
bit stream.
 The design is converted into bit stream and are dumped into a FPGA board using a dumping cable.
 12.The output of the board is connected to a computer via a USB cable where the output is displayed by
using a software called “Tera Term”.
 IMPLEMENTATION OF ETHERNET

The Board used is Kintex-7

1.Open VIVADO

2.Start - All Programs - Xilinx Design Tools – VIVADO.

Select Create New Project.

3.Click Next.

4.Set the Project name and location.

– Check Create Project Subdirectory.

5.Select RTL Project.

Select Do not specify sources at this time.

6.Select the board and click select.

7.Click on IP Catalog.
8.Select Tri Mode Ethernet MAC v8.3 under Communication & Networking.
9.Right click on Tri Mode Ethernet MAC.
– Select Customize IP.
10.Make the following settings
– Set Component Name.
– Set the Board Interfaces:
– ETHERNET: rgmii
– MDIO: mdioio
– Click Interface Tab
11.Make the following settings
– Set Component Name.
– Set the Board Interfaces:
– ETHERNET: rgmii
– MDIO: mdioio
– Click Interface Tab
12.Make the following settings
– De-select Half Duplex, AVB, Frame Filter, and Statistics Counters.
– Click OK.
13.Click Generate.
14.Ethernet design appears in Design Sources.
– Wait until checkmark appears on project.
15.Click on Generate Bitstream.
16.The FPGA board is connected to a computer using an USB cable.
17.Now the bit stream is dumped into the FPGA board.
18. The outputs are displayed on the computer by using wireshark software.
19.Open Wireshark.
– Set the Filter to: eth.addr == da:01:02:03:04:05; click Apply.
– Select the Ethernet NIC and click Start.
20.Open your Network and Sharing Center control panel Click on Change adapter settings.
21. Now the ethernet design runs on the computer.
THANK YOU