2 COE305 - Chapter 2 Programming Model 1

Chapter 2
The Microprocessor and its Architecture
The Intel 8086, 80X86, and Pentium Family
Brey: The Intel Microprocessors, 7e © 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.
Contents
• Internal architecture of the Microprocessor:
– The programmer’s model, i.e. the registers model
– The processor (organization) model
• Memory addressing with segmentation
- In the real mode
- In the protected mode
• Memory addressing with paging
Objectives for this Chapter
• Describe the function and purpose of program-
visible registers
• Describe the Flags register and the purpose of
flag bits
• Describe how memory is accessed using
segmentation in both the real mode and the
protected mode
• Describe the program-invisible registers
• Describe the structures and operation of the
memory paging mechanism
• Describe the organizational processor model
• Briefly review the evolution of the 80X86
architecture
The Intel Family Addressable
Memory, bytes
= 2A
(A)
 (1978)
 (2000)
Increase Increase
Programming
Model
General Purpose
Registers
Special Purpose
Registers
Segment
80386 and above:
Registers
-32-bit registers (except seg. regs.)
-Two additional segment registers:F,G
General-Purpose Registers
• The top portion of the
programming model contains the
general purpose registers:
EAX, EBX, ECX, EDX, EBP, ESI,
and EDI
• Can carry both Data & Address
offsets
• Although general in nature, each
has a special purpose and name:
• EAX – Accumulator
Used also as AX (16 bit),
AH (8 bit), and AL (8 bit)
• EBX – Base Index often used to
address memory (BX, BH, and BL)
General-Purpose Registers
(continued)
• ECX – count, for shifts,
rotates, and loops (CX, CH,
and CL)
• EDX – data, used with
multiply and divide (DX,
DH, and DL)
• EBP – base pointer used to
address stack data (BP)
• ESI – source index (SI) for
memory locations, e.g. with
string instructions
• EDI – destination index (DI)
for memory locations
Special-Purpose Registers
• ESP, EIP, and EFLAGS
Each has a specific task
– ESP – Stack pointer: Offset to the top of the
stack in the stack segment. Used with
procedure calls (SP)
– EIP – Instruction Pointer: Offset to the next
instruction in a program in the code segment
(IP)
– EFLAGS – indicates latest conditions (state) of
the microprocessor (FLAGS)
Used With
SS
CS
EFLAGS
80386DX
Determined by
The Flags last operation
Basic Flag Bits (8086 etc.): Output, Input bits

• C – Carry/borrow from last operation Set/Reset
• P – the parity flag (little used today) explicitly by the
• A – auxiliary flag Half-carry between bits 3 and 4, programmer
used with BCD arithmetic
• Z – zero Some flag bits can be both,
• S – sign e.g. the C flag
• O – Overflow
• D – direction - Determines auto increment/decrement direction
for SI and DI registers with string instructions
• I – interrupt - Enables (using STI) or disables (using CLI) the
processing of hardware interrupts arriving at the INTR input pin
of the processor
• T – Trap - Turns trapping interrupt (for program debugging)
on/off
Newer Flag Bits
• IOPL – 2-bit I/O privilege level in protected mode
• NT – nested task
• RF – resume flag (used with debugging)
• VM – virtual mode: multiple DOS programs each
with a 1 MB memory partition in Windows
• AC – alignment check: detects addressing memory
on wrong boundary for words/double words
• VIF – virtual interrupt flag
• VIP – virtual interrupt pending
• ID = CPUID instruction is supported
The instruction gives info on CPU version and manufacturer
Segment Registers
Each register points to the start of a segment in memory
• The segment registers are:
– CS (code),
– DS (data),
– ES (extra data. used as destination for some string instructions),
– SS (stack),
– FS, and GS: Additional segment registers on 80386 and above
• Segment registers define the start of a section (segment)
of memory for a program.
• A segment is either:
- 64K (216) bytes of fixed length (real mode), or
- Up to 4G (232) bytes of variable length (protected mode).
• All code (programs) reside in a code segment.
Real Mode Memory Addressing
• Used by the DOS operating system
• The only mode available on the 8086-8088:
20 bit address bus  1 MB, 16 bit data bus, 16 bit registers
• Real mode memory is the first 1M (220) bytes of the memory
system (real, conventional, DOS memory) in later processors
• Real mode 20-bit addresses are obtained by combining a
segment number (in a segment register) and an offset address
(in another processor register)
• The segment register address (16-bits) is appended with a 0H
or 00002 (or multiplied by 10H or 16d) to form a 20-bit start of
segment address
• Then the effective memory address (EA) =
this 20-bit segment start address + the 16-bit offset address in
another processor register
• For the 8086, segment length is fixed @ 216 = 64K bytes
(determined by the size of the offset registers)
(11MB)
MB
EA (Effective Address) of byte accessed
20-bit (5-byte) 64 KB +
Physical Segment 16-bit each
Memory address
Appended 4 bits (0H)

Segment number
In Segment Register
Effective Address Calculations
• EA = segment register (SR) x 10H + offset
(a) SR: 1000H
10000 + 0023 = 10023
(b) SR: AAF0H
AAF00 + 0134 = AB034
(c) SR: 1200H
12000 + FFF0 = 21FF0
Q: Is 3FC81 a valid start address of a segment?
Overlapping segments
How to detect overlap?
Top of CS:
090F0
FFFF+
190EF
Code should be limited to only

this portion of the code
segment, to avoid
Brey: The Intel Microprocessors, 7e © 2006 Pearson Education, effects
Upper Saddleof segment
River, NJ 07458. Alloverlap
Rights Reserved.
Defaults
Convention Example: EA = CS:[IP]
• Default segment numbers in:
– CS for program (code) Segment number Offset: Literal
– SS for stack in Segment register or in a CPU register
– DS for data
– ES for string (destination) data
• Default offset addresses that go with them:
Segment Offset (16-bit) Offset (32-bit) Purpose

8080, 8086, 80286 80386 and above
IP EIP Program
CS
SP, BP ESP, EBP Stack
SS
BX, DI, SI, 8-bit or 16-bit # EBX, EDI, ESI, EAX ECX, Data
DS EDX, 8-bit or 32-bit #
DI, with string instructions EDI, with string instructions String
ES destination
Segmentation: Pros and Cons
Advantages:
• Allows easy and efficient relocation of code and data
• To relocate code or data, only the number in the relevant
segment register needs to be changed
Consequences:
A program can be located anywhere in memory without making
any changes to it (addresses are not absolute, but offsets
relative to start of segments)
Program writer needs not worry about actual memory structure
(map) of the computer used to execute it
Disadvantages:
• Complex hardware and for address generation
• Address computation delay for every memory access
• Software limitation: Program size limited by segment size
(64KB with the 8086)
Limitations of the above real mode
segmentation scheme
• Segment size is fixed at and limited to 64 KB
• Segment can not begin at an arbitrary memory
address…
With 20-bit memory addressing, can only begin at
addresses starting with 0H, i.e. at 16 byte intervals
 Principle is difficult to apply with 80286 and above,
with segment registers remaining at 16-bits!
Append: 00H 0000H
80286 and above use 24, 32 bit addresses but still

16-bit segment registers
• No protection mechanisms: Programs can overwrite
operating system code segments and corrupt them!
 Use memory segmentation in the protected mode

Protected Mode Segmentation:
Primarily, what is needed:
• Flexible definition of segment starting address

• Flexible definition of segment size
• Protection mechanisms that prevent programs from
corrupting the code and data of each other and of the
operating system:
Basic Segmentation in the Protected Mode
(Processor) (Memory)
Address Translation
(Segment
Register) (Offset
Register)
Segment Descriptor Table
Table
Access
Maximum
Allowed
Offset
Segment Descriptor Segment

Scheme also checks Start
Offset Address
for privileges and access rights
 Seg number to prevent programs from corrupting
other programs or the operating
system
Protected Mode: 80286 and above
• Domain of the Windows operating system
• 32-bit addressing: 4G of memory with 2G for the system
and 2 G for the application
• Protected mode still uses segment and offset addresses, but:
- Segment definition is through a more complex
selector/descriptor mechanism (greater flexibility)
- Offset address: 16-bit (286) or 32-bits (386 and above: e.g.
EIP register)
• Descriptors are placed in descriptor tables in main memory
• Protection is provided by restricting access to memory
segments through:
- Privilege levels,
- and Access rights
Descriptors specify memory segments
• Segment number (still in a 16-bit segment register)
defines the segment through a selector/descriptor
(not directly as in real mode  but more flexibility)
• 16 bits segment register = 13 bit descriptor selector
+ 1 bit descriptor table selector + 2-bit requested
privilege
Segment How many segments
Register, can be defined in total?
e.g. DS
(1 Table, Segments available to all tasks)
(1 table for each task, segments local to each task)

213 = 8192
Each 8-byte segment descriptor entry in the table contains:
• Base address (start address of segment) (size = mP address bus)
• Limit (maximum offset, i.e. offset for the end address of
segment) (segment size = 1 + Limit)
• Privilege level and access rights to this segment
So a segment can start at any location & have a specified length.

Contains 2-bit 8-byte Segment Descriptors Instruction Segment
Mode: 16/32 bits Availability
Descriptor Privilege Level
LSB
LSB
Max Limit <
Base: 3-byte  24 bit addressing Max offset
Max Limit =
Max offset
Base: 4-byte  32 bit addressing
Limit: 2-byte (16 bit)  Seg. Size: 1B-64 KB
Limit: 2 1/2-byte (20 bit)  Size: 1B-1MB
Note provision for upward compatibility
With G (4 K multiplier) bit = 1: 4KB-4GB
(286Thesoftware
Brey: run on
Intel Microprocessors, 7e higher processors) © 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.
Protected Mode: 80386 and above (Pentium class)
• The base is a 32-bit address at
which the memory segment starts
• The limit is a 20-bit number. When
added to the base, it addresses the
last location in the segment
• The limit has a modifier bit called
Granularity (G). If G=0: no change
• If G=1, append limit with FFFH, i.e.
segment size is multiplied by 4K
• With limit specifying 1 MB
segments and G=1 (i.e. 4K
multiplier): Max Segment size =
4K x 1 MB = 4 GB
• With 16K segments like this, the
system can address 16K x 4 GB =
64 TB (not necessarily all will be in
physical memory)
80386 and above Example:
• Descriptor has: base = 23000000H
limit = 012FFH
With G = 0
Segment start = 23000000H
Segment end = 23000000H + 012FFH=230012FFH
Segment size = 12FFH+1H = 1300H
(= 19 x 256 bytes)
With G = 1 ( so actual limit = 012FFFFFH)

(append limit in descriptor by FFFH)
Segment start = 23000000H
Segment end = 23000000H + 012FFFFFH = 242FFFFFH
Segment size = 12FFFFF+1H = 1300000H = 212 x 1300H
= 4K x 1300H
Protected Mode Segmentation Example
Protected Mode Processor: 80286
Segmentation Example
(in main memory) 24-bit Address
Because each descriptor in
the table is 8 bytes wide,
Selector:000b
is used as an offset
from GDT (or LDT)
base address
to point to the start Always 0’s for
of the required upward Descriptor # 2
segment descriptor compatibility
Access 8-byte Segment Segment size
Descriptor # 1
Rights byte = Limit+1
Limit = FF+1
MSB
Base Offset = 100H bytes
16-bit
Segment
Register H
000b
Descriptor # 0
What is the RPL value?
What is the selector value? GDT Base Address
Are we using the global or the local descriptor?
table?
(= segment #)
The Access Rights Byte: 80286 & higher*
This is the access rights byte

W * 80386 and higher
/R in the 8-byte segment descriptor
have 4 more access
yet rights bits
E: Not Code (0) or stack
00: or Code (1)
Highest
Privilege Not Code ED = Expand Direction
Segment for the segment
Code
Segment DPL will be compared with
the request privilege level
(RPL) in the segment register
specifying this segment.
Allow access to the

segment only if RPL has
higher or equal privilege
to the DPL, subject to the
state of C bit if applicable
Privilege Levels
00: Highest Privilege
01
10
11: Lowest Privilege
Highest
RPL Hardware
(In Seg Reg)
Privilege
Comparator RPL  DPL
DPL Allow
(in descriptor)
Access
to segment
Lowest
Types of Descriptor Tables in memory
• One Global Descriptor Table (GDT): (64 KB Max) (Start and Limit are cached in GDTR)
1. Descriptors for all global segments (common to all tasks)

(cached on the processor for the currently used 6 segments- CS,…GS)
2. For each task:

 Descriptor for the task’s task state segment (TSS) in memory
The TSS holds all information about the task e.g. processor registers, LDT selector, etc.
(descriptor is cached on the processor for the currently running task- selected by TR register)
 Descriptor for the task’s Local Descriptor Table (LDT) in memory:

The LDT holds descriptors for all local segments for that task.
(descriptor is cached on the processor for the currently running task- selected by LDTR
register)
• One Interrupt Descriptor Table (IDT): (64 KB Max) (Start, Limit cached in IDTR)
8-byte descriptors called “interrupt gates” that define the attributes and starting addresses of the
interrupt service routines for up to 256 hardware and software interrupts
• Several local segment descriptor tables, one table for each task. The GDT contains descriptors
for these tables as mentioned in 2 above.
Types of Descriptor Tables in memory
Segment Register
Offset
i
16-bit
Segment # i
Selectors Base, Calculate
Limit, Physical Addressed Byte
LDTR Access
Address
for Seg i
Memory
8-byte System:
Descriptors
Code,
Data,
For each Task Stack,
Extra
Segments
Base,
Limit,
Access One LDT table for each task
Interrupt Descriptor for LDT j
number
for task 0 for task j
…..
(table base address, limit)
Program Invisible Registers (caches)
In main memoryInvisible mP Registers (not seen by programmer)
Segment Descriptor
Descriptor cache for the currently used 6 segments
Loaded
from GDT
or LDT tables
In memory
Visible Segment Selector every time
mp registers the segment
number
changes
Task Cache for the task state segment (TSS) and the descriptor of the local segment
Register descriptor table - for the currently executing task Loaded
from the GDT
Task Selector Task’s TSS In memory
every time
LDT Selector Task’s LDT the task
changes
Global
LDT Register
(for the GDT and IDT tables)
Descriptor
Table (GDT) GDT (24 or 32 bits) GDT (16-bit)
for: segments,
tasks, and LDT
Descriptor
Table for
interrupts
LDT for a task is accessed© through

Brey: The Intel Microprocessors, 7e
a descriptor in the GDT
2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.
Addressing Modes Summary
Addressing Modes Summary
Organizational Model of the Processor
- Functional aspects- how the processor actually functions
- Internal organization is determined by functionality required
Two main tasks for the microprocessor in a mp-based system:
1. Interface with external peripherals
2. Execute instructions
External Buses
Control bus
Microprocessor-based
System; e.g. a microcomputer
Memory I/O Devices
The 8086 processor model (Organization)
• Early pipelining attempts
• Two main functional units:
- The Bus Interface Unit (BIU)
- The Execution Unit (EU)
• The BIU generates memory and I/O addresses for reading code
and transferring data to/from the processor
• The EU receives code and data from the BIU, executes the
instructions, and stores results in the general purpose registers
• Pipelined architecture:
Two, hopefully independent operations, are executed at the
same time by two separate units:
- Fetch by the BIU
- Execute by the EU
& Control
External mp busses
The 8086 processor model FIFO

Instruction/Operand Queue
Interfacing: (BIU) BIU fills it
by fetches
• Generate all timing & control from
signals for reads, writes, etc. memory
• Synchronize data transfers
With all system modules
EU empties it
Execution: (EU) by executing
instructions
• Recognize, decode, and
execute fetched program
instructions
ALU
Has no direct interaction

WithTheexternal
Brey: mp busses
Intel Microprocessors, 7e EU BIU
© 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.
The 8086 processor model
Non-pipelined 
b. Start fetching at
2. Fetch Wasted fetches the correct target
operand after a Jump inst. location
Pipelined
(8086)
a. Oops! Turned c. Execute

1. Operand 3. Execute
Fetch-Execute Overlap not in Queue
out to be a Jump at last!
instruction!
* = Wasted Fetches and Executes (inefficiency)
RISC & Modern architectures:
• Reduce fetches from memory
Common Scenarios that cause pipeline (operate mostly on registers)
inefficiency: • Speed up memory fetches (cache)
• Use small instructions (both in
• Operand is not in queue length and in execution time)
• Jump or branch instructions  Finer pipeline stages (super
• Long-executing instructions: pipelined- 486)
e.g. 83 clock cycles for execution vs. 4  Multiple pipelines (superscalar- P5)
cycles for a fetch.
BIU fills the buffer and waits idly!
 Predict how the jump will go
Brey: The Intel Microprocessors, 7e (branch
© 2006 Pearson Prediction)
Education, Upper Saddle River, NJ 07458. All Rights Reserved.
Evolution of the 80X86 Intel Processors
0.25:1
2-stage
1 execution pipelining
unit
0.5:1
Super pipelining 5-stage

pipelining
Super scalar 2 execution

P5 units
5-stage
pipelining
Increase
Pentium Pro, Pentium II, III

3 execution
units Greater
12-stage
pipelining
Throughput, e.g.
Multi-core Architecture; in MIPs, MFLOPs
e.g. Itanium® 2: Multiple processors on chip
Main
Memory
Super pipelining
EU
On Chip
Example: 486 Processor Model

Example: 486 Processor Model
Colored units are new additions
Chapter 2 Summary
• Described the mP programming model and purpose
and function of program-visible registers
• Described the Flags register and the purpose of
each flag bit
• Described how memory is accessed using
segmentation, both in the real mode and the
protected mode
• Described the program-invisible registers
• Described the structures and operation of the
memory paging mechanism
• Described the organizational model of the 8086 mP
• Reviewed the evolution of the 80X86 architecture:
Pipelining  Super pipelining  Super scalar 
Multi core

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Chapter 2

The Microprocessor and its Architecture

The Intel 8086, 80X86, and Pentium Family

Basic Flag Bits (8086 etc.): Output, Input bits

EA (Effective Address) of byte accessed

Appended 4 bits (0H)

How to detect overlap?

Code should be limited to only

Segment Offset (16-bit) Offset (32-bit) Purpose

80286 and above use 24, 32 bit addresses but still

 Use memory segmentation in the protected mode

Primarily, what is needed:

• Flexible definition of segment starting address

Segment Descriptor Segment

(1 Table, Segments available to all tasks)

(1 table for each task, segments local to each task)

So a segment can start at any location & have a specified length.

With G = 1 ( so actual limit = 012FFFFFH)

This is the access rights byte

Allow access to the

1. Descriptors for all global segments (common to all tasks)

2. For each task:

 Descriptor for the task’s Local Descriptor Table (LDT) in memory:

LDT for a task is accessed© through

The 8086 processor model FIFO

Has no direct interaction

a. Oops! Turned c. Execute

Super pipelining 5-stage

Super scalar 2 execution

Pentium Pro, Pentium II, III

Example: 486 Processor Model

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