CHALLENGES DUE TO SHRINKING

MOSFETS

R. Udaiyakumar
Department of ECE
Sri Krishna College of Technology, Coimbatore
641042
Email: udaicbe42@gmail.com
 IC Evolution (1/3)
 SSI – Small Scale Integration (early 1970s)
 contained 1 – 10 logic gates
 MSI – Medium Scale Integration
 logic functions, counters
 LSI – Large Scale Integration
 first microprocessors on the chip
 VLSI – Very Large Scale Integration
 now offers 64-bit microprocessors, complete with cache
memory (L1 and often L2), floating-point arithmetic unit(s),
etc.

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 IC Evolution (2/3)
 Bipolar technology
 TTL (transistor-transistor logic)
 ECL (emitter-coupled logic)
 MOS (Metal-oxide-silicon)
 although invented before bipolar transistor, was initially difficult to
manufacture
 nMOS (n-channel MOS) technology developed in 1970s required
fewer masking steps, was denser, and consumed less power than
equivalent bipolar ICs => an MOS IC was cheaper than a bipolar IC
and led to investment and growth of the MOS IC market.
 aluminum gates are replaced by polysilicon by early 1980
 CMOS (Complementary MOS): n-channel and p-channel MOS
transistors => lower power consumption, simplified fabrication
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process
IC Evolution (3/3)
 Bi-CMOS- hybrid Bipolar, CMOS (for high speed)

 Ga As - Gallium Arsenide (for high speed)

 Si-Ge - Silicon Germanium (for RF)

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Trends in VLSI
 Transistor
 Smaller, faster, use less power
 Interconnect
 Less resistive, faster, longer (denser design)
 Yield
 Smaller die size, higher yield

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VLSI Trends: Moore’s Law

 In 1965, Gordon Moore predicted that transistors would

continue to shrink, allowing: I’m smiling
 Doubled transistor density every 18-24 months
because I
was right!
 Doubled performance every 18-24 months
 History has proven Moore right
 But, is the end is in sight?
 Physical limitations
 Economic limitations

Gordon Moore
Intel Co-Founder and Chairman Emeritus
Image source: Intel Corporation www.intel.com

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When the chip’s down…

 With feature size shrink of 2 (typical generation)

 2x #transistors/unit area
 2x Higher speed (fmax)
 Fixed cost per wafer
 Smaller (2x), Faster (2x), cheaper – strong economic
driving force
 30% improvement in cost per function per year
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Important challenges
Due to
 Physical

 Material

 Power-Thermal

 Technological

 Economical

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Physical challenges
 These are due to the increment of tunneling and
leakage currents as the devices are becoming smaller,
thus impacts the performance and functionality of
CMOS devices.

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 Material Challenges
 These basically come from the inability of the dielectric
and wiring materials to provide reliable insulation and
conduction, respectively with continued scaling.

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Power-Thermal Challenges
 These are because of the ever increasing number of
transistors integrated per unit-area, which demands
larger power consumption and higher thermal
dissipation.

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Technological Challenges
 These are the results from the incompetency of
lithography based techniques to provide the resolution
below the wavelength of the light to manufacture to
CMOS devices.

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Economical Challenges
 These are mainly due to the rising in cost of production,
fab, and testing that may reach a point where it will be
not affordable from economic point of view.

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Scaling
 The process of shrinking the layout in which every
dimension is reduced by a factor is called Scaling.

 Transistors become smaller, less resistive, faster,

conducting more electricity and using less power.

 Designs have smaller die sizes, higher yield and

increased performance.

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Can Scaling Continue?
 Some characteristics of the transistors do not scale
uniformly, e.g., delay, leakage current, threshold
voltage, etc.

 Mismatch in the scaling of transistors and interconnects.

Interconnect delay has increased from 5-10% of the
overall delay to 50-70%.

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 These trends have brought many
changes and new challenges to circuit
design.

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MOSFETs
Polysilicon Gate
SiO2
Insulator L D
W
Source Drain
G SB G
p+ p+
channel

n substrate S substrate connected

to V DD

Key feature: p transistor

transistor length L 2002: L=130nm
2003: L=90 nm
Polysilicon Gate
SiO2
L D D
2005: L=65 nm
Insulator
W 2008: L=45 nm
Source Drain
G SB G 2013: L=16 nm
n+ n+
channel
p substrate S S
substrate connected
n transistor to GND

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Transistor Switch Model
 NMOSFET or n transistor L L
 on when gate H OFF ON
when gate=L
when gate=H
 "good" switch for logic L L
L
 "poor" switch for logic H L H
 "pull-down" device

 PMOSFET or p transistor OFF ON

when gate=H
when gate=L
 on when gate L H H
 "good" switch for logic
H H L
 "poor" switch for logic L
29 October "pull-up" device
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CMOS Logic Design
 Complementary transistor networks
 Pull-up: p transistors
 Pull-down: n transistors
VDD

VDD
Pullup
Network
(p-transistors)

Inputs Out In Out

Pulldown
Network
(n-transistors)
Gnd

Gnd Inverter
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MOSFET Operation Animation Step 1: Apply Gate Voltage

SiO2 Insulator (Glass)

Gate
Source Drain
5 volts

holes N N

electrons
P

electrons to be
transmitted
Step 3: Channel becomes saturated
Step 2: Excess electrons surface in with electrons. Electrons in source
channel, holes are repelled. are able to flow across channel to
Drain.

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Important Parameters in MOSFETs
Oxide capacitance(Cox) is the capacitance per unit area between the gate metal
and the bulk surface.
Gate-source voltage(Vgs) is the voltage that applied between gate and source to
control the operation of the transistor.
Drain-source voltage(Vds) is the voltage which is applied between drain and
source.
Threshold voltage(Vth) is the minimum voltage that will induce inversion layer
which turn on the transistor.
Drain-source current(Ids) is the current that flow between drain and source
through the inversion channel conducted beneath the gate when transistor is turned
on.
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Complicated Design
 Too many transistors and no way to handle them manually.

 Solutions:

 CAD

 Hierarchical design

 Design re-use

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Power and Noise
 Huge power consumption and heat dissipation becomes a
problem

 Noise and cross talk.

 Solution:

 Better physical design

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Interconnect Area
 Too many interconnects

 Solutions:

 More interconnect layers (made possible by Chemical-

Mechanical Polishing)

 CAD tools for 3-D routing

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Interconnect Delay
 Interconnect delay becomes a dominating factor in circuit
performance
 Solutions:
 Use copper wire
 Interconnect optimization in physical design, e.g., wire
sizing, buffer insertion, buffer sizing.

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Power dissipation
 Current devices have dissipation of the order of 100 W or more

 Heat dissipation, High load current, Packaging cost, Battery

life (for portable systems)

 Pressing need for Power reduction at all levels

 Architectural techniques

 Gate and device level techniques

 Leakage power reduction

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Future directions
 CMOS will dominate in the immediate future
 Current focus on power reduction and interconnect delay
 Three dimensional CMOS
 More focus on architecture
 Frequency scaling has reached the limit
 Multicore systems, Parallel architectures, Reconfigurable
systems etc
 Devices
 Nanotubes
 Spintronics
Molecular structures etc
 2019
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 Concerns for Nano-CMOS
integration

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Concerns for the integration

 Too huge power consumption, heat generation?

 Too huge variations in transistor characteristics, which could make the circuit
design impossible?

 Too many number of transistors for the circuit designers to manipulate?

(design crisis)

 No merit of transistor downsizing in performance and power, because of C

and R of interconnect cannot be reduced

 Who will pay the huge production cost?

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Power and heat increase
Maybe, it is not efficient to increase the clock frequency and number of
transistors
There will not be a big merit without improving the operating
frequency of board or package, and reduce the power consumed there.
Main job of my PC is editing of the document and accessing to internet.
Such an extremely high clock frequency should not be necessary.
Improvement of PC algorithm such that using file searching method of
Google will save the power very much.
Downsizing of Printed Circuit Board will also save the power.

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Variation of Transistor characteristics
System and circuit design will assume such variation.

If too huge variation, Reconfigurable circuit and system design can avoid such
transistors with huge variations. ECC（Error Correction Code) will helps a lot.

Cannot suppress the variation under certain level, but we can offer as many
transistors as the designers want.

It is also important to use the larger device in the circuit, depending on the
usage.

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Design crisis for human power
We could expect the progress of CAD.
Then, we can do only whatever we can design in that period with the
given manpower.
Multi-level system/circuit design, such as multi-core of microprocessor
will save the human power, for example.

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Interconnect R & C
It has been continuously said from 2 or 3 μm generations that
interconnects limit the downsizing. But fortunately, it has never happened
before.

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Huge development and production cost

Leading edge company in memory, microprocessor, DSP, foundry make huge profit.
They should cover the cost.
Leading edge company will pay the cost.
Otherwise they will drop off from the existent race, and the competitor will be very
happy.
2nd and 3rd tier companies could enjoy the reduced cost of the development and
production, but no big profit.
They cannot be too late to proceed to the downsizing, because China will catch up
soon.

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Nanoscale MOSFETs

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High-k Dielectrics in Gate Stack
 As the gate length shrinks in the
technology node, the gate oxide
leakage current increases with
decreasing SiO2 thickness.

 The use of SiO2 in gate stacks is

limited by already approximately one
monolayer .

 High-k dielectrics such as HfO2, offer

a thicker oxideURL:http://www.research.ibm.com/journal/rd/433/
without degrading campbell.html

gate capacitance.
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High-k/Metal Gate Transistors
 High-k / poly- Si gate MOSFETs have challenges:

 Degraded channel mobility.

 Higher threshold voltage.

 High-k / Metal gates:

 Reduced mobility degradation addressed by SiO2 layer

underlying HfO2.

 Offers lower dielectric leakage.

 High-k dielectrics are typically more compatible with non-

silicon substrates (e.g., Ge).
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HfO2 Gate Stack Modeling
 High-k metal oxides are being used as SiO2 replacements to minimize gate
leakage.
 HfO2 has promising properties and can be integrated into current process
streams.
 For process integration and speed, desirable to simultaneously etch entire
gate stack…Success with Ar/BCl3/Cl2 plasmas.
 Challenge:
 Modeling is required to speed process development and optimization.
 There exists no fundamental database for process.
 Develop mechanism based on experience and data from literature.

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Nanometer challenges
 Current generation feature size is 16nm
 Shrinking of gate oxide causes tunneling leading to gate
leakage
 High fields produce large leakage current
 Interconnect delays dominate over gate delays
 As wires shrink resistance increases thereby increasing
delay
 May offset speed benefits of scaling
 Low K dielectrics
 Power density and heat dissipation
 Very crucial issue
 Power density rising at a rapid pace
 Leakage Power increases at sub micron dimensions
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contributing a substantial part of the total power
Alternate FET structures
 DGMOSFETs

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 Thanks for your patient Listening
&
Queries???????

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