Basic Computer Architecture

Lecture 1
ATEEQ UR REHMAN
Basic microcomputer design
• clock synchronizes CPU operations
• control unit (CU) coordinates sequence of
execution steps
• ALU performs arithmetic and logic operations
data bus

registers

I/O I/O
Central Processor Unit Memory Storage
Device Device
(CPU) Unit
#1 #2

ALU CU clock

control bus

address bus

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Basic microcomputer design
• The memory storage unit holds instructions and
data for a running program
• A bus is a group of wires that transfer data from
one part to another (data, address, control)
data bus

registers

I/O I/O
Central Processor Unit Memory Storage
Device Device
(CPU) Unit
#1 #2

ALU CU clock

control bus

address bus

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Clock
• synchronizes all CPU and BUS operations
• machine (clock) cycle measures time of a single
operation
• clock is used to trigger events
one cycle

• Basic unit of time, 1GHz→clock cycle=1ns

• An instruction could take multiple cycles to
complete, e.g. multiply in 8088 takes 50 cycles
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How to classify processors
• Categorized by instruction type
– CISC
– RISC

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Memory in those days was expensive
 bigger program->more storage->more money
Hence needed to reduce the number of instructions
per program
Number of instructions are reduced by having
multiple operations
within a single instruction
Multiple operations lead to many different kinds of
instructions that
access memory
 In turn making instruction length variable and
fetch-decode execute
time unpredictable – making it more complex
 Thus hardware handles the complexity

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 What is CISC….?
 A complex instruction set computer
(CISC, pronounced like "sisk") is a
microprocessor instruction set architecture
(ISA) in which each instruction can
execute several low-level operations, such
as a load from memory, an arithmetic
operation, and a memory store, all in a
single instruction.

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 Characteristics of a CISC design

 Register to register, register to memory, and

memory to register commands.
 Uses Multiple addressing modes .
 Variable length instructions where the length
often varies according to the addressing mode
 Instructions which require multiple clock cycles
to execute.

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RISC Design Principles
• Simple operations
– Simple instructions that can execute in one cycle
• Register-to-register operations
– Only load and store operations access memory
– Rest of the operations on a register-to-register basis
• Simple addressing modes
– A few addressing modes (1 or 2)
• Large number of registers
– Needed to support register-to-register operations
– Minimize the procedure call and return overhead

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RISC Design Principles
• Fixed-length instructions
– Facilitates efficient instruction execution
• Simple instruction format
– Fixed boundaries for various fields
• opcode, source operands,…

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CISC and RISC
• CISC – complex instruction set
– large instruction set
– high-level operations (simpler for compiler?)
– requires microcode interpreter (could take a long
time)
– examples: Intel 80x86 family
• RISC – reduced instruction set
– small instruction set
– simple instructions
– directly executed by hardware very quickly
– easier to incorporate advanced architecture design
– examples: ARM (Advanced RISC Machines) and DEC
Alpha (now Compaq), PowerPC, MIPS
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Example of CPU Architectures
• Intel: 80x86
• Motorola: 680x0 CISC

• Sun : Sparc
• Silicon Graphics : MIPS
• HP : PA-RISC
• IBM: Power PC
• Compaq: Alpha RISC

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CISC and RISC

CISC RISC
(Intel 486) (MIPS R4000)
#instructions 235 94
Addr. modes 11 1
Inst. Size (bytes) 1-12 4
GP registers 8 32

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