Fpga Vs Asic Design Flow

FPGA vs.
ASIC Design Flow
FPGA and ASIC Technology © 2009 Xilinx, Inc. All Rights Reserved
Comparison - 1
Intro to VHDL or 3
Intro to Verilog days
FPGA and ASIC
Technology
Comparison
Curriculum FPGA vs.

ASIC Design
Path Flow
ASIC to FPGA
Coding
Conversion
Virtex-5 Coding
Techniques
Spartan-3 Coding
Techniques
Fundamentals of 1 for
FPGA Design day
ASIC Design
Designing for 2
Performance day
s
Advanced FPGA 2
Implementation days
Welcome
If you are an experienced ASIC designer

transitioning to FPGAs, this course will help
you reduce your learning curve by
leveraging your ASIC experience
Careful attention to how FPGAs are different
than ASICs will help you create a fast and
reliable FPGA design
After completing this
module, you will able to:
Describe key differences between ASIC and

FPGA design flows, including
 Design methodology
 Verification techniques
 Test-generation logic
 Tools
Design Flow
ASIC and FPGA design and implementation
methodologies differ moderately
Xilinx FPGAs provide for reduced design time and later
bug fixes
• No design for test logic is required
• Deep sub-micron verification is done
• No waiting for prototypes
Coding style
For high-performance designs, FPGAs may require
some pipelining
When retargeting code from an ASIC to an FPGA, the
code usually requires optimization (instantiation)
FPGA and ASIC Technology © 2009

2007 Xilinx, Inc. All Rights Reserved
Comparison - 5
ASIC Design Flow
ASIC tools are generally driven by
scripts
Post-synthesis static timing
analysis and equivalency checking
are musts for sign off to foundry
Verification of deep sub-micron
effects (second- and third-order
effects) is required for ASICs
Internal, deep sub-micron effects
are already verified for Xilinx
FPGAs

Comparison - 6
FPGA Design Flow
FPGA tools are generally
GUI-driven, pushbutton flows
FPGA tools also have scripting
capabilities
After the design passes behavioral
simulation and static timing analysis,
verification is completed most efficiently
by verifying in circuit
Fast turnaround times
Static timing analysis is used to verify
timing of the design
Timing simulation is supported
This is a simplified/typical design flow

Comparison - 7
ASIC Implementation
Create HDL
Optimized for ASIC technology and
area
Synthesis
Primarily driven by scripts
Synopsys design compile
Design for test logic insertion
(BIST, Scan, and JTAG)
Place & route
Foundry tools, Cadence, AVANT

Comparison - 8
FPGA Implementation
Create HDL
Optimized for Xilinx FPGAs and
performance
Synthesis
Synopsys, Mentor, XST
Pushbutton flow with
scripting capabilities
Place & route
Completed by the user
Xilinx implementation tools – ISE® software
Pushbutton flow, scripting capabilities

Comparison - 9
ASIC Verification
Key ASIC verification points
Behavioral simulation*
Post-synthesis static timing analysis
Post-synthesis equivalency checking
Post-place & route static timing analysis*
Post-place & route equivalency checking
Post-place & route timing simulation*
Verification of second- and third-order
effects
Verify in circuit*
* Applies to both FPGA and ASIC design

flows
Comparison - 10
FPGA Verification
Three key verification points for FPGA
implementation
Behavioral simulation
Post-place & route static timing analysis
Download and verify in circuit
Post-synthesis gate-level simulation
and post-place & route timing simulations
can be done for production sign off
Post-place & route timing
simulations are also often done
to verify board- and system-level timing

Comparison - 11
Deep Sub-Micron Effects
Second- and third-order effects
Silicon-induced design flaws due to the small
wire delays and narrow silicon of deep sub-
micron processes
They include cross talk, interconnect delays,
and Simultaneously Switching Outputs (SSO)
Xilinx FPGAs inherently have fewer deep sub-
micron silicon issues
Pre-engineered standard product alleviates
complex deep sub-micron design issues
Recovers design innovation time and
facilitates time-to-market

Comparison - 12
Design for Test Logic
ASIC test-generation logic is not required
in a Xilinx FPGA
Because of the capability to test in-circuit,
automatic test pattern generation logic is
normally not included
• This reduces the time spent on creating and
inserting test logic, and allows more time to be
spent “on the bench” testing the design
Xilinx FPGAs already contain JTAG (boundary scan) logic
Xilinx FPGAs have readback capability that is similar to scan logic
Readback can verify the configuration as well as the internal status of
registers and memory

Comparison - 13
In-Circuit Verification Tools
ChipScope Pro software
Integrated Logic Analysis (ILA)
provides in-circuit logic
verification through the
dedicated JTAG pins
No need for extra headers
The ChipScope Pro software is
a standalone tool for logic
analysis
Data channels from 1 to 256;
sample sizes from 256 to 4096

Comparison - 14
Firmware Development
ASIC Design Flow
Firmware development begins much earlier
in the design cycle for FPGAs
No waiting time for prototypes
Hardware and software can develop in
tandem

Comparison - 15
Design Flow Comparison
ASIC FPGA

Comparison - 16
Advanced FPGA Tool Flow
Equivalency checking
Synopsys Formality
Floorplanning and layout
Synopsys Amplify (physical synthesis)
Xilinx Floorplanner or PlanAhead™ software
Static timing analysis
Synopsys PrimeTime
Calculating power use
Xilinx XPower
Edit routing and placement
Xilinx FPGA Editor

Comparison - 17
PROPERTIES
On passing, 'Finish' button: Goes to Next Slide
On failing, 'Finish' button: Goes to Next Slide
Allow user to leave quiz: After user has completed quiz
User may view slides after quiz: At any time
User may attempt quiz: Unlimited times
Equivalency Checking
Equivalency checking (also known as formal verification) determines if
two versions of a design are functionally equivalent
For example, an RTL versus a post-synthesis design
Fast and efficient verification of large designs without the use of test vectors
• Far faster than simulating post-synthesis and post-place & route netlists

Comparison - 19
Floorplanning and Layout
The Floorplanner utility and
PlanAhead software are used for
design layout

Comparison - 20
ISE Tool Floorplanner
Grey
Placement
window shows
Design Hierarchy the placement
Displays color- found by the
coded hierarchical implementation
blocks tools
Design Nets
Highlights a selected net White Floorplan window
in the design shows the area constraints
you have made
Comparison - 21
PlanAhead Software
Challenging designs
Large devices, complex constraints, heavy utilization
Designs experiencing implementation issues
Performance, capacity, run time, and repeatability
Significant run-time reductions realized after
floorplanning
Designs requiring implementation control
Users looking for options other than pushbutton flow
Visualize design issues from many aspects
Block-based designs Virtex®-4 FX140 FPGA
• 24 clock domains
Module-level incremental updates • 2 processors
Provides an IP reuse solution • 1760 I/Os
• Many resource types
Comparison - 22
PinAhead
Pin assignment analysis
Tool includes a DRC
check and WASSO Properties, Device View
Package View
analysis Selection Views
Allows you to see both a

Package and Pin view of Clock Regions View
your design
I/O Ports View
Makes it easy to make

pin assignments and Package Pins View
attributes

Comparison - 23
Xilinx SmartGuide Technology and
Partitions
SmartGuide™ technology is used to maintain as much of the place &
route as possible, while still enabling place & route changes to improve
timing
Works best when there are small design changes and the original design
met timing
Saves place & route run time
Partitions are used to maintain a place & route solution for unmodified
logic in a partition
Works best if you have large amounts of design changes between each
iteration
Works best if a single partition has a high percentage of changes
Timing-critical paths should not cross any boundaries
Saves place & route run time

Comparison - 24
FPGA Editor
The FPGA Editor is a graphical
application that displays
Device resources
Precise layout of the chosen
device
The FPGA Editor is commonly
used to
View device resources
Make minor modifications
• Done late in the design cycle
• Does not require re-
implementation of the design
• Changes are NOT back-
annotated to the source files
Insert probes
Make short-term functional
FPGA andchanges for in-circuit verification
ASIC Technology © 2009
Comparison - 25
Xilinx XPower
XPower is used to estimate
the power consumption and
junction temperature of
your FPGA
Reads an implemented
design (NCD file) and
timing constraint data
You supply activity rates,
clock frequencies, capacitive
loading on output pins,
power supply data, and
ambient temperature
• You can also supply design activity data from simulation (VCD file)

Comparison - 26
Synopsys PrimeTime
PrimeTime is a full-chip static timing analysis

tool targeting complex multimillion gate designs
Ideal for system-on-a-chip designs
PrimeTime provides ASIC-quality sign off of
multimillion-gate FPGAs

Comparison - 27
PROPERTIES
On passing, 'Finish' button: Goes to Next Slide
On failing, 'Finish' button: Goes to Next Slide
Allow user to leave quiz: After user has completed quiz
User may view slides after quiz: At any time
User may attempt quiz: Unlimited times
Summary
FPGAs provide for reduced design time and later bug fixes
No design for test logic is required
Deep sub-micron verification has been completed
No waiting for prototypes
• Firmware development starts sooner in the design cycle for the FPGA design
flow
• Faster production ramp up
Xilinx provides powerful tools for advanced control over implementation
The Xilinx ChipScope Pro software tool provides powerful in-circuit
verification

Comparison - 29
Where Can I Learn More?
Xilinx online documents
www.support.xilinx.com
• Virtex-5 FPGA User Guide (Detailed architecture information)
• Virtex-5 FPGA Packaging and Pinout Specifications (Pinout tables, PCB design rules,
etc.)
• Virtex-5 FPGA Configuration User Guide (Configuration overview, JTAG, readback, etc.)
Xilinx Training
www.xilinx.com/training
• ChipScope Pro software course
• PlanAhead software course
• Timing Analyzer is taught in the Designing for Performance course
• FPGA Editor, Floorplanner, SmartGuide technology, and partitions are taught in the
Advanced FPGA Implementation course
• Free recorded e-Learning modules
ChipScope Pro and PlanAhead software are add-on products
www.support.xilinx.com/chipscopepro
Both are free for 60 days
Comparison - 30
End of Design Flow
You have completed
FPGA vs. ASIC Design Flow.
The next course in the ASIC curriculum sequence is
ASIC to FPGA Coding Conversion, Part 1
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Comparison - 31
Trademark Information
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assistance provided to you in connection with the Design.
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Comparison - 32

Fpga Vs Asic Design Flow

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FPGA vs.

ASIC Design Flow

Curriculum FPGA vs.

If you are an experienced ASIC designer

Describe key differences between ASIC and

FPGA and ASIC Technology © 2009

FPGA and ASIC Technology © 2009

FPGA and ASIC Technology © 2009

FPGA and ASIC Technology © 2009

FPGA and ASIC Technology © 2009

* Applies to both FPGA and ASIC design

FPGA and ASIC Technology © 2009

FPGA and ASIC Technology © 2009

FPGA and ASIC Technology © 2009

FPGA and ASIC Technology © 2009

FPGA and ASIC Technology © 2009

FPGA and ASIC Technology © 2009

FPGA and ASIC Technology © 2009

FPGA and ASIC Technology © 2009

FPGA and ASIC Technology © 2009

Allows you to see both a

Makes it easy to make

FPGA and ASIC Technology © 2009

FPGA and ASIC Technology © 2009

FPGA and ASIC Technology © 2009

PrimeTime is a full-chip static timing analysis

FPGA and ASIC Technology © 2009

FPGA and ASIC Technology © 2009

More FPGA Courses

FPGA and ASIC Technology © 2009

FPGA and ASIC Technology © 2009

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