CprE 281:

Digital Logic

Instructor: Alexander Stoytchev

http://www.ece.iastate.edu/~alexs/classes/
Serial Adder

CprE 281: Digital Logic

Iowa State University, Ames, IA
Copyright © Alexander Stoytchev
 Administrative Stuff
• Homework 10 is out

• It is due on Monday Dec 2, 2013

 Administrative Stuff
• Extra Credit Homework #2 is out

• Posted on the class web page

• There are 4 problems

• Due no later than the last lab for this semester

• Submit your design on paper and demonstrate your

circuit to the lab TAs using the boards in the lab.
 Administrative Stuff
• Final Project

• Posted on the class web page (Labs section)

• Pick one of the 4 problems and solve it.

• Your grade will not depend on which project you pick

• By this Friday you need to select your project

number and e-mail that number to your lab TAs
 Sample E-mail
Hello TAs,

I decided to pick problem number x for my final

project in CprE 281.

Thanks,

[your name]
The general form of a synchronous sequential circuit

W Combinational Combinational
Flip-flops circuit Z
circuit Q

Clock

[ Figure 6.1 from the textbook ]

 Moore Type

W Combinational Combinational
Flip-flops circuit Z
circuit Q

Clock
 Mealy Type

W Combinational Combinational
Flip-flops circuit Z
circuit Q

Clock
Moore Mealy
Moore Mealy
Mealy

Moore
Mealy

Moore
This is delayed by
1 clock cycle
 A

a
Shift register
s
Adder
FSM Shift register
Shift register
b
Sum = A + B
B
Clock

Figure 6.39. Block diagram for the serial adder.

 Reset ab  s 
11  0

00  0 01  0
01  1 G H 10  0
10  1 11  1

00  1

G: carry-in = 0
H: carry-in = 1

Figure 6.40. State diagram for the serial adder FSM.

 Present Next state Output s
state ab =00 01 10 11 00 01 10 11
G G G G H 0 1 1 0
H G H H H 1 0 0 1

Figure 6.41. State table for the serial adder FSM.

 Next state Output
Present
state ab =00 01 10 11 00 01 10 11
y Y s
0 0 0 0 1 0 1 1 0
1 0 1 1 1 1 0 0 1

Figure 6.42. State-assigned table for Figure 6.41.

 a s
Full
b
adder Y y
D Q
carry-out

Clock Q

Reset

Figure 6.43. Circuit for the adder FSM in Figure 6.39.

 Reset

11 01
00 G0 s = 0 H0 s = 0
10

00
01 00 11 01
10 11 10

01 G1 s = 1 H1 s = 1 11
10 00

Figure 6.44. State diagram for the Moore-type serial adder FSM.
 Present Nextstate Output
state ab =00 01 10 11 s
G0 G0 G1 G1 H0 0
G1 G0 G1 G1 H0 1
H0 G1 H0 H0 H1 0
H1 G1 H0 H0 H1 1

Figure 6.45. State table for the Moore-type serial adder FSM.
 Nextstate
Present
state ab =00 01 10 11 Output
y2 y1 s
Y2 Y1
00 00 01 01 10 0
01 00 01 01 10 1
10 01 10 10 11 0
11 01 10 10 11 1

Figure 6.46. State-assigned table for Figure 6.45.

 Sum bit Y1 y1
a D Q s
Full
b
adder Carry-out
Q

Y2 y2
D Q

Clock Q

Reset

Figure 6.47. Circuit for the Moore-type serial adder FSM.

Questions?
THE END