Clock Gating Checks

Active High Clock Gating

Active High Clock Gating
 Gating signal
changing in Active
high region

Here one can observe that if

the enable signal changes
during active high clock edge
there we can see that clock is
getting twice for one
transition in enable signal.
That is wrong because for the
transition in enable we need
to store the data for that
entire clock cycle. But here for
us since the clock is simply
getting triggered it wont be
storing the correct data
 Gating Signal
Changing in active low
clock period

Here in this case we will see

the pulses of width half the
clock period, which can trigger
the fanout flop normally.

And by putting some setup

and hold checks to the pulses
in the enable signal one can
remove the glitches
 Setup and Hold
checks

• For setup check the enable

signal need to be stable
before some time of the
rising edge of the clock .
• For hold check, the enable
signal needs to be stable for
some time after the falling
edge of the clock.
• Note: Hold is not time
stable after rising edge.If so
we will be seeing unwanted
clock pulses
• Active High Clock gating means ,when the enable signal becomes high
the clock signal passes through the gating cell.
• For active high clock gating the enable signal need to be varying only
in the active low period of clock cycle. Otherwise we will see
unwanted pulses.
 A clock of period 1 ns . Half time period is 500 ps.
Setup time= AAT-RAT
##Setup:
report_at -pin cg1_1:a –late –rise #enable
path worst arrival time
361
Example Report_at –pin cg1_1:b –early –rise #clock path
best arrival time
42
Setup slack : 361<=1000+42-0 => slack =1042-
361= 681 ps
 Hold slack = RAT-AAT
report_at -pin cg1_1:a –early –rise #enable path best
arrival time
87
Report_at –pin cg1_1:b –late –rise #clock path worst
arrival time
67
Contd. Hold slack : 87>67 => slack =87-67= 20 ps (wrong)
Hold slack: 87-(67+500)=> slack= -480 ps (correct)
Because the clock path arrival time is wrt the falling edge of
the clock signal, so that is equal to the half period of the
clock.
 Or
Report_at –pin cg1_1:b –late –fall #clock path
best arrival time
Now it will be 567
Contd.. Slack = 87-567 = -480ps
Note: The hold check is wrt the falling edge of the
clock, so that’s the reason extra 500 ps got added
in the clock arrival time
Sample timing reports

Here Enable path started at

0ps because @ rise edge

And for clock path it started at

10ps.Since it is setup check we
will be checking at the next
clock edge
 Contd..

• Here we can clearly see that

for hold also enable starts at
0ps @riseedge
• But for clock it starts at 5 ps,
@fall edge

• Hold is enable signal being

stable after the fall edge for
the active high case.
Here we can see that setup is clean and
hold is violating.
• And we can also observe that there is sufficient
setup margin to clean the hold violation as well.
• So by buffering the net on the enable data path
one can delay the data path and fix the hold
violation.
• Or by squeezing the setup margin simply by
making the launch flop as neg triggered flip
flop.This method doesnot need huge buffering of
the net, which might cause more drcs if in
congested area.
Method 2 by changing the launch flop as neg
edge triggered
Timing report
for the
modified
ckt:Setup
Enable data path fall edge @5ps

Clock path next edge @10 ps

 Hold report

• Enable data path fall edge@

5ps
• Clock path fall edge @5ps
Active Low Clock Gating
Active Low clock Gating
 Active Low Clock
Gating Waveform

• For Setup check the data in

enable signal need to be
stable some time before
the clock edge
• And for hold the data in the
enable net need to be stable
for some time after the
clock edge
 Timing Report for
Active Low Clock
Gating

Data path @ 0 ps
Clock path @ 4 ps falledge
Hold report for active
low clock gating

This is as usual one for data it

is @0ps
And for clock at the same
edge so @0ps
Clock Gating with Mux
• Since the clock gating cell is a multiplexer the clock gating check is not
inferred automatically . So one can manually force that check to be
clock gating check by the following command.
Set_clock_gating_check -high [get_cells UMUX0]
Set_disable_clock_gating_check UMUX0/I1 #because for clock gatimg
cell one clock pin and one enable pin . So therefore we are disabling
the clock gating path through the I1 pin . So here the clock gating check
is only for the MCLK
 Timing reports Setup

Since the clock is inverted it is

at 5 ps at data path

And for clock path that is

MCLK and since setup we will
see at the next clock edge that
is @10ps
Hold Timing report for
mux based

Data path @ inverted so @

5ps

Clock path @ 5ps since this is

equivalent to the active high
clock gating
Clock Gating with clock inversion
 Timing reports

Setup: 5 ps since the clock is

inverted

And 15 ps in the clock path

since the next clock edge
 Hold report

Hold:
data path: 5 ps since inverted
clock

And 10ps in clock path since

this is equivalent to the active
high clock gating because
there is and gate.