MICROPROCESSOR SYSTEMS AND

INTERFACING (EEE342)
Dr. Nadia Nawaz
8086 VS 8088 MICROPROCESSORS

8086 MICROPROCESSOR 8088 MICROPROCESSOR

The data bus is of 16 bits The data bus is of 8 bits

It has 3 available clock speeds It has 2 available clock speeds

(5 MHz, 8 MHz, and 10 MHz) (5 MHz, 8 MHz)

The memory capacity is implemented as a

The memory capacity is 512 kB
single 1 M x 8 memory banks

It has complemented memory control pin

It has memory control pin (M/IO) signal
(IO/M) signal of 8086

It has Bank High Enable (BHE) signal It has Status Signal (SSO)

It can read or write either 8-bit or 16-bit It can read only 8-bit word at the same
word at the same time time

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GENERAL BUS OPERTION

 The 8086 multiplexed address and data bus

 The bus can be demultiplexed using a few latches and transceivers

 The negative edge of the ALE pulse is used to separate the address and
the data or status information
 In maximum mode, the status lines S0, S1 and S2 are used to indicate the
type of operation
 Status bits S3 to S7 are multiplexed with higher order address bits and the
BHE signal.
 Address is valid during T1 while status bits S3 to S7 are valid during T2
through T4.

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THE 8088 AND 8086 MICROPROCESSORS (CONT.)

Pin layout of the 8086 and 8088 microprocessor

MINIMUM-MODE AND MAXIMUM-MODE SYSTEM (CONT.)

Common Pin functions

Most pins are independent and serve a single function
Examples:
• CLK—clock
• INTR—interrupt request
• READY—bus ready

Some multi-functions pins–different times/different mode

Examples:
• AD0-AD15– multiplexed address/data lines at different times
• A16/S3—multiplexed address and status line at different
times
• IO/M or S2 Control line in one mode or bus status line in other
mode

Signals common to both minimum and maximum mode

TWO OPERATING MODES OF 8088/8086.

• Minimum mode—small system/single processor configuration

• Maximum mode—large system single multi-processor configuration
• Hardware connection at MN/MX pin 33 selects mode
• 1 = +Vcc = Minimum mode
• 0 = GND = Maximum mode
• 8088 signals/pins categorized as
• Common—same function both modes
Examples: Pin 9 (AD7)- pin 16 (AD0)
• Minimum Mode—special minimum mode operations
Examples: pins 26-28 are DEN, DT/R, and IO/M
• Maximum Mode—special maximum mode operations
Example: pins 26-28 are S0, S1, and S2.

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MINIMUM-MODE AND MAXIMUM-MODE SYSTEM (CONT.)

Unique minimum-mode signals

MINIMUM-MODE AND MAXIMUM-MODE SYSTEM (CONT.)

Address bus status codes

Unique maximum-mode signals

MINIMUM MODE INTERFACE

 Block diagram of the minimum-mode 8086 and 8088 MPU

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MINIMUM-MODE INTERFACES– 8088 INTERFACE
 MPU provides all of the interface signals
 Address/data bus
 Status
 Control
 Interrupt
 DMA
 Multiplexed address/data bus
 20-bit address (A19-A0) 1MByte address space
 8-bit data bus (D7-D0)
 Signals of the address/data bus
 AD0-AD7—bi-directional, tri-state
 Lower 8 address output lines
 8 bi-directional data bus lines
 A8-A15—output, tri-state
 Next 8 address lines
 A16/S3-A19/S6—output, tri-state
 Four most significant address
lines
 S3–S6 status signals
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MEMORY/IO CONTROL SIGNALS
o Support signals for controlling the  RD* = read active 0
memory and I/O interface circuitry  Signals that a read/input bus cycle is
• All but READY are outputs in progress
o ALE= address latch enable  WR* = write active 0
• Signals external circuitry that a valid address in on the  Signals that a write/output bus
address bus and it should be latched cycle is in progress
o IO/M* = IO/memory  DEN* = data enable active 0
o Identifies type of data transfer taking place over the  Signal when the data bus should be
data bus; used to enable/disable memory and/or IO enabled
interface
 READY = ready
o IO/M* = 1 = input/output data  1= Acknowledges that the memory
o IO/M* = 0 = memory data subsystem is ready to complete the
bus cycle
o DT/R* = data transmit/receive  0= Memory subsystem is not ready;
o Tells external circuitry which way data is to be insert wait sates to extend the bus
transferred over the bus; used to set direction of data cycle
bus interface  SSO* = status
circuits
 0= instruction code read
o DT/R* = 1 = transmit  1= data access
mode(write/output)
o DT/R* = 0 = read mode (read/input)
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 INTERRUPT INTERFACE
 Support signals for implementing an
interrupt driven I/O interface
 Maskable interrupt interface—INTR and
INTA*
 Nonmaskable interrupt interface—NMI
 Reset interface—RESET
 INTR = interrupt request input active 1
(level triggered)
 External device signals the MPU that it
needs maskable interrupt service
 INTA* = interrupt acknowledge output
active 0
 MPU acknowledges to an external devices
that its maskable interrupt request is being
serviced
 NMI = nonmaskable interrupt input
 External device initiates NMI request with
0 to 1 transition (edge triggered)
 RESET = reset input active 1
 Logic 1 initiates hardware reset of MPU
 Initializes internal registers and reset
service routine
DMA INTERFACE
 Support signals for implemented a
direct memory access interface
 Permits direct transfer of
information between parts of
memory or between memory
and I/O devices.
 External devices, such as a DMA
controller, perform these operations
independent of MPU
 HOLD= Hold request input active 1
(level triggered)
 External device request the MPU give it
control of the system bus
 HOLDA* = Hold acknowledge output
active 1
 MPU tri-states its bus lines
 Acknowledges to an external
devices that the MPU bus is in
the hold state
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MINIMUM MODE -8086 INTERFACE
 Data bus (16-bit wide)
 D15-D0
 Multiplexed with A15 through A0
 Allows 3 types of data transfers
 Word—over D15-D0
 Low byte—over D7-D0
 High byte—over D15-D8
 Memory/IO Controls
 SSO* ->BHE* (bank high enable)
 Used to signal external circuitry whether or not a byte
transfer is taking place over the upper 8 data bus lines
 A0 now does the same for a byte transfer over the lower 8
data bus line

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MAXIMUM-MODE INTERFACE
 In maximum-mode, MPU does not directly provide all the signals
 𝑊𝑅, 𝐼𝑂/𝑀,ഥ DT/𝑅, ത 𝐷𝐸𝑁, ALE, and 𝐼𝑁𝑇𝐴 signals are no longer produced by the 8088
 Three signal lines 𝑆0 , 𝑆ഥ1 , 𝑆2 identifies which type of bus cycle is to follow
 MRDC – Memory Read Command
 MWTC – Memory Write Command
 AMWC – Advanced Memory Write Command

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MAXIMUM-MODE INTERFACE

 8086 and 8088 maximum-mode block diagram

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MAXIMUM-MODE INTERFACE
 8288 bus controller

 Block diagram and pin layout of 8288

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HARDWARE ORGANIZATION OF THE MEMORY ADDRESS SPACE

 1Mx8 memory bank of the 8088

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HARDWARE ORGANIZATION OF THE MEMORY ADDRESS SPACE

 High and low memory banks of the 8086

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HARDWARE ORGANIZATION OF THE MEMORY ADDRESS SPACE

 Byte transfer by the 8088

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HARDWARE ORGANIZATION OF THE MEMORY ADDRESS SPACE

 Word transfer by the 8088

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HARDWARE ORGANIZATION OF THE MEMORY ADDRESS SPACE

 Even address byte transfer by the 8086

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HARDWARE ORGANIZATION OF THE MEMORY ADDRESS SPACE

 Odd address byte transfer by the 8086

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HARDWARE ORGANIZATION OF THE MEMORY ADDRESS SPACE

 Even address word transfer by the 8086

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HARDWARE ORGANIZATION OF THE MEMORY ADDRESS SPACE

 Odd-address word transfer by the 8086

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HARDWARE ORGANIZATION OF THE MEMORY ADDRESS SPACE

 EXAMPLE
 Is the word at memory address 0123116 of an 8086-based microcomputer aligned or
misaligned? How many cycle are required to read it from memory?
 Solution:
 The first byte of the word is the second byte at the aligned-word address 0123016.
Therefore, the word is misaligned and required two bus cycles to be read from
memory.

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EXAMPLES

 Given an overview of how a byte of data is read from memory address 0xB0003
of an 8088-based microcomputer, and list the memory control signals along with
their active logic levels that occur during the memory read bus cycle
 Solution:
 Address 0xB0003 is applied over the lines A0 through A19 of the address bus, and a byte
of data is fetched over data bus lines D0 through D7.
 Only one bus cycle is required
 To read a byte from memory. Control signals in minimum mode at the time of the read
are
 A0= 1
 𝑊𝑅 = 1
 𝑅𝐷 = 0
 𝐼𝑂/𝑀ഥ =0
 DT/𝑅ത = 0
 𝐷𝐸𝑁 = 0

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EXAMPLES

 Given an overview of how a word of data is written to memory starting at

address 0xA0000 of an 8088-based microcomputer, and list the memory control
signals along with their active logic levels that occur during the memory write
bus cycle
 Solution:
 Two bus cycles must take place to write the word of data to memory. During the first bus
cycle, the least significant byte of the word is written to the byte storage location at
address 0xA0000. Next the 8088 automatically increments the address so that it points to
the byte storage location 0xA0001. The most significant byte of the word is written into
this storage location with a second write bus cycle. During both bus cycles, address
information is applied to the memory subsystem over address lines A0 through A19 and
data are transferred over data bus lines D0 through D7. The minimum mode control
signals during the write are:
 𝑊𝑅 = 0
 DT/𝑅ത = 1
 𝐷𝐸𝑁 = 0
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MEMORY CONTROL SIGNALS

 Minimum-mode memory control signals

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MEMORY CONTROL SIGNALS (CONT.)

 Maximum-mode memory control signals

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CLOCK GENERATOR 8284A

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LATCHING AND BUFFERING

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BUS CYCLE
 Microprocessors use the memory and I/O in periods called bus cycle.
 A bus cycle defines the basic operation that a microprocessor performs to
communicate with external devices.
 Examples of bus cycles are memory read, memory write, input/ output read
and input/ output write.
 A bus cycle corresponds to a sequence of events that starts with an address
being output on the system bus followed by a read or write data transfer
 During these operations, a series of control signals are also produced by the
MPU to control the direction and timing of the bus.
 Each bus cycle consists of at least four clock periods, T1, T2, T3, and T4.
 These clock periods are also called the T- States.
 If the clock is operated at 5MHz(0.2ųs) then one bus cycle is completed in
800ns.
 This means that the MP reads or writes data between itself and memory or
I/O at a max rate of 1.25 million times a second
 Clock Cycle

Read Data Read Data

Check READY
(Normal) (with Wait)

 T1 - start of bus cycle. Actions include setting control signals (or S0- S2 status lines) to give
the required values for ALE, DT/ R, IO/ M putting a valid address onto the address bus.

 T2 - the RD or WR control signals are issued, DEN is asserted in the case of a write, data is
put onto the data bus. The DEN turns on the data bus buffers to connect the CPU to the
external data bus, so memory or I/O can receive the data to be written. The READY input to
the CPU is sampled at the end of T2 and if READY is low, a wait state TW (one or more) is
inserted before T3 begins.

 T3- this clock period is provided to allow memory to access the data. If the bus cycle is a read
cycle, the data bus is sampled at the end of T3.

 T4- all bus signals are deactivated in preparation for the next clock cycle. The 8088 also
finishes samples the data bus connections for data (in a read cycle) in this period. For the
write cycle, the trailing edge of the WR signal transfers data to the memory or I/ O, which
activates and write when WR returns to logic 1 level.
MINIMUM MODE 8088 BUS TIMING FOR A READ OPERATION
READ AND WRITE BUS CYCLE

 Read cycle

 Minimum-mode memory read bus cycle of the 8088

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READ AND WRITE BUS CYCLE

 Read cycle

 Minimum-mode memory read bus cycle of the 8086

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SIMPLIFIED WRITE CYCLE
WRITE BUS CYCLE

 Write cycle

 Minimum-mode memory read bus cycle of the 8088 and 8086

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READ AND WRITE BUS CYCLE

 Write cycle

 Maximum-mode memory read bus cycle of the 8086

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TIMING IN GENERAL: READ & WRITE WITH WAITS
WK 5 Read Cycle with 1 TW Write Cycle with 1 TW
X X
TW TW

Latch Sample the READY I/P Latch

Address Address
Muxed
Lines

mP strobes data in
HiZ

, #INTA

Data
IN
Buffer OUT
Direction

Enable Address O/P Data Address O/P Data

Data
Buffers
WR
Note: #RD,#WR,#INTA Device strobes data in

are all inactive high during T1