‫‪Maze Routing‬‬

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 Improving Lee’s Algorithm
• The choice of the starting pin can affect the speed of
the algorithm,
– one guideline is to start on the pin farthest from the center of
the chip

• Use double fan out

- begin at both pins and continue until a point of contact is
made

• Use framing,
– an artificial rectangular boundary 10 to 20% larger than the
boundary formed by the pins

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 Schemes to Reduce Run Time
1. Starting Point Selection:
T S
S T

2. Double Fan-Out: 3. Framing:

S S
T T

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 Multi-Terminal Nets

• For a k-terminal net, connect the k terminals

using a rectilinear Steiner tree with the least
wire length on the maze.
• This problem is NP-Complete!
• So, just want to find some good heuristic.
• This problem can be solved by extending the
Lee’s algorithm. Any idea …..

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 Connecting Multipoint Nets

• One point is selected as the source and all the

other points are the target
– propagate from the source until one target is
reached
– find the path from the source to that target
– all the cells on the path are labeled as source cells
and the remaining unconnected pins are targets
– repeat the steps

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 Example
4 3 2 1 2113 24 53 4
3 2 1 S 1 2 13 24 53 4
4 3 22 1 12 3 41 25 3 4 T
5 44 3 2 13 4 51 2 3 4
54 43 32 14 5 1 2 3 4
4 53 42 15 T 1 2 3 4
4 53 2 1 2 3 4

Start at the source and run the maze router until you hit a target
Every cell on the path is a source – run the maze router
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 Hadlock’s Algorithm
to Reduce Run Time

“A Shortest Path Algorithm for Grid

Graphs”, F.O. Hadlock, Networks,
7:323-334, 1977.

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 Hadlock’s Algorithm
Detour Number: For a path P from S to T,
d(P) = # of grids directed away from T, then
L(P) = MD(S,T) + 2d(P)
Length
Manhattan Distance

D D
D: Detour
D
S d(P) = 3
MD(S,T) = 6
T L(P) = 6+2x3 = 12

So
17 minimizing L(P) and d(P) are the same.
‫مرتضي صاحب الزماني‬
 Hadlock’s Algorithm
• Label vertices with detour numbers
instead of distance.
• Vertices with smaller detour number
are expanded first.
• Therefore, favor paths without detour.

3 2 2 3
2 1 1
1 S 0
1 0 0
1 0 0 2 T
2 1 1 2 2
3 2 2 2 2 2
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 Hadlock’s Algorithm

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 Multilayer Routing

• Give a system with multiple wire layers

– Parallel grids vertically stacked, one for each layer
– Use vias to access other layers
– Label cells as to whether a via is permitted at its
location

• How do we find wire paths in such a structure?

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 Multilayer Routing

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 Aside: VIAs
• Vias:
– “Vertical” electrical connection

• Issue: size
– On chips, vias are usually a lot bigger than wire widths so you
have to be careful where you put them
– You can’t put vias as close to each other as you can put wires

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 Example
• Given two metal layers with vias allowed in some cells
(labeled as ‘v’)
3 2 3 4 5 5
2 1 2 3 4 5 5 4 5
Expansion 3 3
may go up 1 S 1 2 v 4 5 5 4 v 4
and down 2 1 2 3 4 5 5 4 5
as well as 3 2 3 4 5 5 5
to adjacent 4
cells 4 3 vv4 5 5 v 5 T
5 4 5 5
5

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Layer 1 ‫صاحب الزماني‬
Layer 2 ‫مرتضي‬
 References

• David Pan, VLSI Physical Design

Automation, Lecture Slides, University of
Texas, 2009.

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