A.

C Theory & Electronics

Flip-flops
 Ponder this for a moment!
• Success is the sum of small efforts,
repeated day in and day out.
Robert Collier

• CAPE Physics Unit 2 – Exam Dates

– Paper 2: May 29,2012 – Morning
– Paper 1: May 31, 2012 – Afternoon
 Flip-flops
• A flip-flop is a bistable multivibrator that can
store information.
• A bistable is a device that has two stable states
and it can be switched or ‘flipped’ between the
two states.
• Essentially the flip-flop is a digital latch that will
store a binary digit for a controlled length of
time. Flip-flops are also known as sequential
circuits in which the output is determined by both
the input at a particular time and the previous
outputs. Flip-flops have two outputs Q and.
There are three basic types of flip-flops:
• Set-Reset (S-R),
• D-type, and
• JK.
The Set-Reset type is the simplest.
 S-R flip-flop constructed with NAND gates

•If the Set and Reset inputs are both LOW (zero), the outputs will both be HIGH.
•Because Q and Q are always the inverse of each other, the flip-flop is said to be
in an ambiguous state (invalid state) when Set = 0 and Reset = 0.
•Set and Reset are usually resting in the HIGH state and one of the
inputs will be pulsed LOW whenever the output is required to change.
• When Set = Reset = 1, the present output is
determined by the previous output
• When S = 0, R = 1, Q goes high. Whenever Q is
HIGH, the flip-flop is said to be SET. Q will
remain high until R is changed to zero.
• When S = 1, R = 0, Q goes low (Q = 0). The flip-
flop is RESET. The Q output will remain latched
in the low state until S = 0.
• When S = 0, R = 0, SET RESET simultaneously
produces an ambiguous state. This combination
cannot be used.
• The Set-Reset flip-flop has only three usable
states.
 Truth Table
S R Q Q̅ State

0 0 1 1 Ambiguous/Invalid
0 1 1 0 Set
1 0 0 1 Reset
No change No change
1 1 Previous

• What number would you put in the “no change” slots?

 S-R flip-flop constructed with NOR gates

•Both NOR and NAND S-R flip-flops have only three usable states.
•The main difference between the NAND S-R flip-flop and the
NOR S-R flip-flop is that the Q output is taken from gate 2.
•The schematic symbols are the same except that the NOR
S-R has no inverters shown at the inputs.
 NOR S-R flip-flop
• When S = R = 1 the Q output and the Q̅
output will both be zero and the flip-flop is
said to be in an ambiguous state
• When S = 1, R = 0 Q will be HIGH and will
remain high after the set input returns to
zero. Because Q = 1 in this condition the
flip-flop is SET.
• When S = 0, R = 1, Q = 0 and will remain
low after the Reset input returns to zero.
Because Q = 0, the flip-flop is said to be
RESET.
 NOR S-R flip-flop

S R Q Q̅ State

0 0 No change No change Previous

0 1 0 1 Reset
1 0 1 0 Set
1 1 0 0 Ambiguous/Invalid
NOR S-R flip-flop
 S-R flip-flop

• The SR flip-flop is able to store one BIT of

information at Q such as 1 or 0.
• It therefore acts as a ONE-BIT MEMORY,
since once Q has been made 1, it will stay
1 until S and R are changed.
• A computer can read the output at any
time and find the output that has been
stored. A computer will have a large
number of flip-flops has its memory.
 Clocked Set-Reset Flip-flop
• The SR flip-flop can be modified to provide
a third input, a clock. The result is a
clocked SR flip-flop. The clock sends out
rectangular pulses which rise and fall
(from low, 0, to high, 1, and back again) at
regular intervals.
• Inputs S & R only affects the output Q and
Q
when the clock input is HIGH.
 Binary Counters
• Binary Counters can be made from a
combination of modified clocked SR flip-
flops.
• The following two modifications are
needed:
– The output Q must change state only as the
clock pulse changes from LOW to HIGH (i.e.
the flip-flop must be ‘edge triggered’).
– The SR flip-flop must be made into a T flip-
flop
 T Flip-flops
• T Flip-flops (Triggered or Toggling Bistable)
are building blocks of binary counters.
• The T Flip-flop has no S input and the output Q
changes state on each rising edge (0 to 1) of the
clock pulse. The RESET (R) input cause Q to go
to 0 regardless of clock state
 T Flip-flops
• The T flip-flop changes its output on each
clock edge, giving an output which is half
the frequency of the signal to the T input.
 Three-Bit Binary Counter
• A three-bit counter can be made from 3 T flip-flops arranged
so that the output from the first flip-flop is connected to the
toggle input, T, of the second flip-flop etc.
• The R connections are connected together so
that R = 1 resets the counter to 000.
• The counter counts the incoming clock pulses
(the input).
• The outputs can be read as signals on LEDs.
Each of the outputs is either dependent on the
state of the input (the clock signal) or the
previous output.
– Q0 is dependent on the input signal, Q1 is dependent
on Q0, and Q2 is dependent on Q1.

• When the input signal goes high (the clock

signal goes high i.e. 0 to 1) the Q0 output
changes state
Three-Bit Binary Counter