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Single-Chip Multi-Processors
(CMP)
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PRADEEP DANDAMUDI
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Microprocessor
Methods To Increase Performance:
• Parallelism
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Parallelism in Microprocessors
• Pipelining is most prevalent
▫ Used in everything
▫ Even microcontrollers
▫ Decreases cycle time
▫ Allows up to 1 instruction per cycle (IPC)
▫ No programming changes
▫ Some Pentium 4s have more than 30 stages!
• Parallelism classifications:
Instruction level
Loop level
Thread level - Future trend
Process level - Future trend
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• Single processor
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Superscalar pipeline
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Competing technologies
• Simultaneous Multi Threading
▫ Simultaneous Multi threading architecture is similar to that of the
superscalar.
▫ SMT processors support wide superscalar processors with hardware, to
execute instructions from multiple thread concurrently.
• Out-of-Order Execution
▫ Where instructions execute in any order that does not violate data
dependencies.
▫ Note that this technique is independent of both pipelining and
superscalar
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Centralized architecture
• Disadvantages of centralized architectures such as SMT and
Superscalars are:
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- Gate density
(More transistors per chip)
- Cost of wires
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CMP Architectures
• Two general types of multi-core or chip multiprocessor (CMP)
architectures
▫ Homogeneous CMPs – all processing elements (PEs) are
the same
▫ Heterogeneous CMPs – comprised of different PEs
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CMP Advantages
• CMPs have several advantages over single processor solutions
▫ Energy and silicon area efficiency
By Incorporating smaller less complex cores onto a single chip
Dynamically switching between cores and powering down
unused cores [5]
▫ Increased throughput performance by exploiting parallelism
Multiple computing resources can take better advantage of
instruction, thread, and process level parallelism
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Summary
• The CMP architecture is now the architecture of
choice for semiconductor manufactures
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References
• http://www.morganclaypool.com/doi/abs/10.2200/S00093ED1V01Y2007
07CAC003
• L Hammond, BA Nayfeh, K Olukotun, “A Single-Chip Multiprocessor,”
IEEE, Sept 1997.
http://occs.ieee.org/presentations/2007/070122_Jenks_ParallelMicroproc
essors.pdf
• Chip Multiprocessor (CMP) Architectures
,web.cecs.pdx.edu/~mperkows/CAPSTONES/DSP1/ELG6163_Burton.ppt
• en.wikipedia.org/wiki/