Sequential Circuits

Inputs Combinational Outputs

circuit Memory
Next elements
state Present
state

Clock
Clock
aa periodic
periodic external
external event
event (input)
(input)
Clock
 Comparison b/w combinational & sequential logic circuits.
combinational
The output variables are at all times
dependent on the combination of input
variables
Memory unit is not required
Faster in speed , because the delay b/w
input & output is due to propagation delay of
logic gates
These are easy to design
It does not have a clock signal
Eg: Adders , subtractors , MUX, DEMUX………
sequential
The output variables dependent not only on
present input variables but also depend
upon the past information
Memory unit is required to store the past
information
Slower than the combinational circuits
These circuits are comparatively harder to
design
It may or may not have a clock signal . Most
sequential circuits have a clock signal
Eg: flip-flops ,counters , shift registers
Classification of sequential logic circuits
(depending on timing of their signals)
Synchronous Asynchronous

The change in input signal can The change in input signal can
effect memory element upon effect memory element at any
activation of clock signal instant of time.

Memory elements are clocked Memory elements are either

flip-flops
The maximum operating speed
of clock depends on time delays
involved
unclocked flip-flops or time
delay elements
Because of absence of clock
asynchronous circuits operate
faster than synchronous circuits

Easier to design More difficult to design

•Memory elements are either latches or flip-flops.
•The main difference b/w latches & flip-flops is in the method
used for changing their state.
•Flip-flop is a logic circuit used to store one bit of binary
information.
•Latch is an unclocked flip-flop.
• Types:
 SR
D
 JK
T
 S-R Latch with NORs
R (reset) Q S R Q Q’
1 10 0 Undefined
1 0 1 0 Set
Q 0 1 0 1 Reset
S (set) 0 0 0 1 Stable
1 0
• S-R latch made from cross-coupled NORs
• If Q = 1, set state
• If Q = 0, reset state
• Usually S=0 and R=0
• S=1 and R=1 generates unpredictable results
 TRUTH TABLE
INPUTS Present Next state STATE
state
S R Qn Qn+1 Qn+1’

0 0 0 0 1 NO
CHANGE
1 1 0
0 1 0 0 1
RESET
1 0 1
1 0 0 1 0
SET
1 1 0
1 1 0 0 0 INDETER
MINATE
1 0 0
 S R Q Q’
S-R Latch with NANDs(ACTIVE
0 0 1 1 Disallowed
LOW):
0 1 1 0 Set
S 0 1 Reset
Q 1 0
1 1 0 1 Store
1 0

Q’
R

• Latch made from cross-coupled NANDs

• Sometimes called S’-R’ latch
• Usually S=1 and R=1
• S=0 and R=0 generates unpredictable results
 inputs Present Next state
state
S R Qn Qn+1 Qn+1’ STATE

0 0 0 1 1 INDETERM
INATE
1 1 1
0 1 0 1 0
SET
1 1 0
1 0 0 0 1
RESET
1 0 1
1 1 0 0 1 NO
CHANGE
1 1 0
S-R Latches
S-R Latch with control input
 Triggering in flipflops
• Level triggering (in latches)
– Positive level triggering
– Negative level triggering
• Flipflops:
– Pulse triggering (+ve & -ve)
– Edge triggering (+ve & -ve)

Hi-Lo edge Lo-Hi edge

Clocked SR Flip-Flop
 TRUTH TABLE

CLOCK S R Qn Qn+1 STATE

(enable)

0 X X X Qn no change

1 0 0 0 0 no change

1 1 1
1 0 1 0 0
RESET
1 1 0
1 1 0 0 1
SET
1 1 1
1 1 1 0 x INDETER
MINATE
1 1 x
 CHARACTERISTIC TABLE
S R Qn+1
0 0 Qn
0 1 0
S
SR 1 0 1
00 01 11 10
Q( t )
1 1 ?
0 0 0 X 1
EXCITATION/APPLICATION TABLE
1 1 0 X 1
Qn Qn+1 S R
R 0 0 0 X
Characteristic Equation: 0 1 1 0
Q+ = S + R’ Q 1 0 0 1
1 1 X 0
 D-Latch C D Q
0 x No change
1 0 0
1 1 1

• Advantages over S-R Latch

– Single input to store 1 or 0
– Avoid spurious input of S=1 and R=1
Clocked D Flip-Flop
• Stores a value on the positive edge of C
• Input changes at other times have no effect on output
Clocked D Flip-Flop
D
3
1 Q

CP Q’
2
4
5
 TRUTH TABLE
CLOCK D Qn Qn+1 STATE
(enable) EXCITATION/APPLICATIO
N TABLE
Qn Qn+1 D
0 X X Qn no
change 0 0 0
1 0 0 0 0 1 1
RESET
1 1 0 1 0 0
1 1 0 1 1 1 1
SET
1 1 1 CHARACTERISTIC TABLE
D D Qn+1
Q 0 1
0 0 1 0 0
1 0 1 1 1
Q+ = D
Clocked J-K Flip Flop
 TRUTH TABLE

CLOCK J K Qn Qn+1 Qn+1’ STATE

0 X X X Qn Qn’ no
change

1 0 0 0 0 1 no
change
1 1 1 0
1 0 1 0 0 1
RESET
1 1 0 1
1 1 0 0 1 0
SET
1 1 1 0
1 1 1 0 1 0 TOGGLE
STATE
1 1 0 1
Asynchronous Inputs
Master-Slave Edge-Triggered Flip-Flop

QM
D Q
Master Slave
Latch Latch
CLK 2 x 8 = 16 Transistors
CLK

CLK

QM

Q
CONVERSION OF FLIPFLOPS
1)SR FLIPFLOP TO D-FLIPFLOP:
INPUT(D) PRESENT NEXT FLIP FLOP INPUTS
STATE(Qn) STATE(Qn+1) S R

0 0 0 0 1
0 1 1 1 0
1 0 0 1 0
1 1 1 0 1

S=D

R=D’
2)SR-FLIPFLOP TO JK-FLIPFLOP:
J K Qn Qn+1 S R
0 0 0 0 0 x
1 1 x 0
0 1 0 0 0 x
1 0 0 1
1 0 0 1 1 0
1 1 x 0
1 1 0 1 1 0
1 0 0 1

R Q Q R = K + Qn
K
S = J + Qn’
J S Q Q
clk
3)D flipflop to JK Flip-Flop

J K Qn Qn+1 D
0 0 0 0 0
1 1 1
0 1 0 0 0
1 0 0
1 0 0 1 1
1 1 1
1 1 0 1 1
1 0 0

D = K’ Qn + J Qn’
D flipflop to JK Flip-Flop

Q
D
K
Latch
Q
CLK
4)Toggle Flip-Flop from D-flipflop
• Toggles stored value if T = 1 when CLK is high

Q
T D
Latch
CLK

T Qn Qn+1 D D = T  Q(t)
0 0 0 0
1 1 1
1 0 1 1
1 0 0